Silicon Debug Research Articles

A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug

Silicon debugging is carried out in multiple sessions which are characterized by run-and-halt intervals. One of the important criteria for the success of this method is that the debugging infrastructure should capture only the erroneous data which can add important insights to the debugging process. However, identification of such suspect clock cycles is not a trivial exercise and requires an systematic approach. We propose a debugging architecture for enhancing the multisession procedure using the technique of on-chip debug data compression. The first session assists in identifying those erroneous clock cycles, and the useful debug data are collected in the second session with the help of markers called tag bits. At the cost of a minimal increase in area overhead, the proposed architecture achieves finer temporal visibility expansion because of the debug data collection in a segregated manner. During the offline analysis of the collected debug data, error localization can be achieved to a finer resolution. We evaluate our methodology on several designs for different kinds of error configurations. Experimental results show that the proposed methodology can achieve better on-chip storage utilization and the expansion in the temporal observation window compared to similar techniques in the literature.

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement

Silicon debugging of integrated circuits is exacerbated by the lack of golden responses, highly restricted observability and irreproducible nature of bugs. Debug engineers need to develop better methods that can assist in error localization at lower level(netlist) granularity. It is widely accepted that root-cause analysis of electrical bugs is highly difficult which further elongates the time needed to fix them. This paper revisits methodologies to debug electrical errors through satisfiability(SAT) solving under a limited visibility environment. We propose various SAT formulations and analyze their efficacy in error localization for a variety of benchmark circuits. The selection of debugging instrumentation is an important issue in post-silicon validation. We analyze different graph-based signal tracing techniques and propose a methodology that utilizes clustering of the nodes of the circuit graph. We aim at minimizing the overhead associated with signal tracing while maintaining the error localization efficacy. We address scalability concerns in SAT solving through partitioning of large error traces. We provide localization results on two different error models (bit-flip and stuck-at) and evaluate its efficiency through a set of different metrics.

IC Debug and Fault Isolation for an Age of IoE and High Data Rates—A Vision

The electronics industry faces an explosion of data collection, exchange and storage for the Internet of Everything, cloud computing, and many more applications. A dramatic performance gain of circuits and systems will be required, including a drastic increase of operating frequency, combined with very low power and low latency—all this at no cost increase. Although the International Technology Roadmap for Semiconductors, representing the progress of Moore’s law, edited their final report in 2016, it can easily be predicted that electronic systems and packages will undergo enormous miniaturization and new interconnect concepts involving new materials and solutions, called “heterogeneous integration.” First silicon debug and diagnosis and failure analysis (FA) rely on internal signal tracking using contactless fault isolation (CFI). CFI is performed from the chip backside utilizing near-infrared optical probe that interacts with the logical signal. This paper assesses CFI readiness for the expected evolution on chip level and system/package level. Challenges and new opportunities will be discussed that CFI encounters with 3-D integration and photonic interconnects. Together with innovations in test, reliability, and security, a vision and several options are presented. They indicate how challenges to CFI may be mastered by new concepts of debug and FA, when they are part of the design concept of the electronic systems from early on.

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

This paper presents the hardware and software architecture of a reusable BIST engine for 3D stacked 14-nm SoC, which also includes softwareassisted autorepair of memory defects. Silicon results presented demonstrate the features of such engine such as easy silicon debug, validation time reduction by 3x, detection and repair of memory cell defects, etc. This solution has been successfully designed and used for seven Intel SoCs successfully debugged, tested, and launched into the market place.

Depositing Controlled, Matched Resistors for Circuit Edit of Analog Circuitry

Abstract During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how to validate it because of the difficulty of the FIB edit required and the inherent uncertainty of the approach. In this article, the authors explain how they came up with an alternative approach that proved to be faster, more reliable, and easier to validate than the cut-and-join fix initially proposed. They describe each step of the analog circuit editing process, explaining how they deposit, characterize, and connect matched resistors using focused ion beam techniques.

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, our method can also be used to characterize the propagation delay across each fault-free interposer wire.

A look at silicon debug and diagnosis [From the EIC

The Editor-in-Cheif is pleased to present this July-August issue, which brings you a combination of articles that cover a rich set of academic and industrial work addressing state-of-the-art issues of design, verification, and test of different IC-based systems represented at different levels of abstraction. The figure of merit for the different approaches varies, depending on the specific case, but are generally variations of cost, performance, quality, yield, and feasibility. An overview of each of the technical articles and features is presented.

Guest Editors' Introduction: Silicon Debug and Diagnosis

The articles in this special section focus on software debugging and diagnosis techniques.

Deconfigurable microprocessor architectures for silicon debug acceleration

The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of "noise" in this phase is that large numbers of random test programs fail due to the same or similar design bugs. This redundant behavior adds long delays in the debug flow since each failing random program must be separately examined, although it does not usually bring new debug information. The development of effective techniques that detect dominant modes of failure among random programs and triage them into common categories eliminate redundant debug sessions and significantly boost silicon debug. We propose the employment of deconfigurable microprocessor architectures along with self-checking random test programs to reduce the redundant debug sessions and make the triage step of silicon debug more efficient. Several hardware components of high performance microprocessor micro-architectures can be deconfigured while keeping the functional completeness of the design. This is the property we exploit in our silicon debug methodology for the triaging of random test programs. We support our methodology by a hardware mechanism dedicated to silicon debug that groups the failing test programs into categories depending on the microprocessor hardware components that need to be deconfigured for a random test program to be correctly executed. Identical deconfiguration sequences for multiple test programs indicate the existence of redundancy among them and group them together. This grouping significantly reduces the number of failing tests that must be debugged afterwards. Detailed evaluation of the method on an x86 microprocessor demonstrates its efficiency in reducing the debug sessions and thus in accelerating silicon debug.

On‐chip support for software verification and debug in multi‐core embedded systems

The challenges in silicon testing and debug of complex integrated circuits are well understood. Where these circuits include multiple processor cores there is also a dramatic increase in the complexity of verifying and debugging the associated software; with much of this complexity being because of the inherent lack of visibility over internal signals which integration brings. The trend to-date has been to rely upon silicon test interfaces to provide access to internal signals required for software verification and debug. However, it is questionable whether this is sufficient for real-time systems or future designs with increasing processor cores. This study examines the on-chip technology supporting software verification and debug in current designs and proposes enhancements in this area. As much of this technology is primarily intended for silicon test it is lacking in terms of I/O bandwidth, which is a significant limitation for software verification and debug. The authors propose their alternative approach of using an on-chip coprocessor and debug circuitry to address this principal limitation; and describe an embedded application where this approach was successfully applied to monitor timing requirements and detect failures. The authors also outline how this approach could be applied as an architectural solution for formal runtime verification.

Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing

Test cost has gradually become a major portion of the overall product cost for System-on-Chips (SoCs). Developing efficient methods to test and debug analog, mixed-signal, and radiofrequency (RF) circuitries is of particular interest due to their lengthy test times and increased complexity. In the past, mixedsignal/RF circuits were built as stand-alone chips, so test developments were geared toward characterizing individual building blocks. With increased integration, the controllability and observability to these mixed-signal/RF circuits has become limited. As a result, built-in self-test (BIST) and design-fortestability (DfT) modifications that can help reduce test time and facilitate silicon debug have gained more attention. This special issue collects 16 state-of-the-art solutions for testing various mixed-signal, RF, and MEMS circuits. The first four papers propose BIST techniques for on-chip mixed-signal, RF, and MEMS modules. In paper 1, Zhang et al. develop an amplitude detector that transforms highfrequency signals into DC/low-frequency components. They then infer high-frequency circuit performance from detectors’ output and show that both the systemand component-level performances can be tested with great accuracy. In paper 2, Hung and Hong propose a BIST scheme for ADCs where the control signals are wirelessly transmitted from an HOY tester. They show that the BIST test results align well with those produced by conventional methods. In paper 3, Kim and Abraham propose a BIST scheme for testing the setup and hold time of the memory interface. They use a static mode test method to determine pass/fail on the timing specifications, as well as a dynamic mode test method to measure the amount of timing mismatch. In paper 4, Sarraf et al. develop an adaptive technique based on pseudo-random sequences for testing and calibrating MEMS-based accelerometers and gyroscopes. Papers 5 to 7 focus on techniques for generating accurate and low-cost test signals. In paper 5, Duan et al. incorporate the “stimulus error identification and removal” (SEIR) algorithm into their BIST solution so that they can test high-resolution ADCs without using high precision stimuli, thereby saving cost. For applications that require time or frequency domain test stimulus, in paper 6, Tsai et al. develop a time/frequency-domain signal generator using a sigma-delta modulator, a digital-to-frequency or a digital-totime converter, and a phase locked-loop. Testing ADCs usually requires high-precision signal generation. In paper 7, Wakabayashi et al. propose an algorithm for generating low distortion sine-wave signals using low-resolution (hence, low cost) waveform generators. Papers 8 to 12 enhance observability of internal analog signals. In paper 8, Kulovic and Margala introduce a technique for on-chip voltage measurement. On-chip voltages are first converted to the time domain, and subsequently, to the frequency domain using a centralized time-to-digital converter. The distributed manner of voltage-to-time conversion enables concurrent voltage measurement. In paper 9, Maltabas et al. propose a current sensor that is suitable for IDDQ measurement. In paper 10, Gomez et al. exploit the relationship between device transconductance and static power dissipation to observe process variations. In paper 11, Dasnurkar and Abraham propose a built-in current sensor that is suitable for measuring internal bias currents. Responsible Editor: H.-M. Chang

On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation

Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification. One effective silicon debug technique is to monitor and trace the behaviors of the circuit during its normal operation. However, due to the associated overhead, designers can only afford to trace a small number of signals in the design. Selecting which signals to trace is therefore a crucial issue for the effectiveness of this technique. This paper proposes an automated trace signal selection strategy with a new probability-based evaluation metric, which is able to dramatically enhance the visibility in post-silicon validation. Experimental results on benchmark circuits show that the proposed technique is more effective than existing solutions.

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

With the growing size of modern designs and more strict time-to-market constraints, design errors can unavoidably escape pre-silicon verification and reside in silicon prototypes. Due to those errors and faults in the fabrication process, silicon debug has become a necessary step in the digital integrated circuit design flow. Embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging. However, the amount of the data is limited compared to pre-silicon debugging. This paper presents an automated software solution to analyze this sparse data to detect suspects of the failure in both the spatial and temporal domain. It also introduces a technique to automate the configuration process for trace-buffer-based hardware in order to acquire helpful information for debugging the failure. The technique takes the hardware constraints into account and identifies alternatives for signals not part of the traceable set so that their values can be restored by implications. The experiments demonstrate the effectiveness of the proposed software solution in terms of run-time and resolution.

Scan Based Silicon Debug

Silicon debug is very important to make a VLSI product quickly available to the market and meet time-to-volume requirement. With designs becoming more complicated, the time spent for silicon debug is taking more fraction of the whole design cycle. Many silicon bugs are found at system level or at chip level while applying a functional test sequence. Comparing to scan test failures, debugging the functional failures is more time-consuming. Scan-based diagnosis is more mature in the recent years and already widely used by many semiconductor companies as defect localization and yield ramp up tool. Meanwhile people have already started to adopt the scan-based diagnosis in silicon debug. Nevertheless, since the objective and application are different in manufacturing diagnosis and silicon debug, their application flows could be also different. In this paper, we will discuss the challenge and possible solutions for using scan-based diagnosis flow on silicon debug.

Enabling Baseline Yield Improvement with Diagnosis Driven Yield Analysis

The time to market of a digital device includes first silicon debug, yield ramp and mature yield improvement. Manufacturing test failures caused by defects during mature yield state are usually hard to characterize for advanced technologies and resemble baseline pattern. Diagnosis driven yield analysis (DDYA) is a solution which can be used efficiently during different stages of product life. Instead of relying on just a handful of high quality diagnosis results, it takes volume layout-aware diagnosis results, performs yield analysis, identifies systematic signature, facilitates root cause analysis, and picks the best candidate die for physical failure analysis (FA). The confirmed PFA result can then be used to adjust fabrication process to improve baseline yield and reduce future occurrences of such failures. Case study in this paper shows this flow helped improve a mature yield by 1.7%.

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

In this paper, a technique is presented for selecting signals to observe during silicon debug. Internal signals are used to analyze, understand, and debug circuit misbehavior. An automated procedure to select which signals to observe is proposed to facilitate early detection of circuit malfunction and to enhance the utilization of hardware resources for storage. Signals that are most often sensitized to possible errors are observed in sequential circuits. Given a functional input vector set, an error transmission matrix is generated by analyzing which flip-flops are sensitized to other flip-flops. Relatively independent flip-flops are identified and a set of signals that maximally cover the possible error sites with given constraints are identified through integer linear programming. Experimental results show that the proposed approach can rapidly and precisely identify the nonconforming chip behavior and thereby can speed up the post-silicon debug process.

High Resolution Application Specific Fault Diagnosis of FPGAs

High resolution diagnosis plays a critical role in silicon debug and yield improvement. Application-dependent diagnosis is also a key component in online testing and adaptive computing. In this paper, a new technique for high resolution localization of faults in the interconnects and logic blocks of an arbitrary design implemented on a field-programmable gate array (FPGA) is presented. This work is complementary to application-independent detection methods for FPGAs. This technique can uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The number of test configurations for interconnect diagnosis is logarithmic to the size of the mapped design, whereas logic diagnosis is performed in only one test configuration with less than 5% overhead of built-in self diagnosis. These techniques have been further extended for multiple fault diagnosis.

All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control

A 45 nm microprocessor integrates an all-digital dynamic variation monitor (DVM) to continuously measure the impact of dynamic parameter variations on circuit-level performance to enhance silicon debug and adaptive clock control. The DVM consists of a tunable replica circuit, a time-to-digital converter, and multiplexers to measure circuit delay or frequency changes with less than a 1% measured resolution error while capturing clock-to-data correlations. In validating the DVM with microprocessor maximum clock frequency (FMAX) measurements, an on-die noise injector circuit induces a supply voltage (VCC) droop at a particular cycle in the test program. The FMAX measurement is then repeated for over a thousand iterations while shifting the droop placement to a different cycle per iteration. Silicon measurements demonstrate the DVM capability of tracking the worst case FMAX reduction to within 1% for a wide range of VCC droop profiles. Furthermore, silicon measurements reveal that FMAX is highly sensitive to the placement and magnitude of a high-frequency VCC droop during program execution, thus highlighting the value of the DVM for silicon debug. In addition, the DVM interfaces with an adaptive clock control circuit to dynamically adjust the clock frequency by changing the divide ratio in the phase-locked loop in response to persistent variations, enabling the microprocessor to adapt to the operating environment for maximum efficiency.

On Using Lossy Compression for Repeatable Experiments during Silicon Debug

The amount of data that is observed during at-speed silicon debug is limited by the capacity of the on-chip trace buffers. To increase the debug observation window, we propose a low-cost debug architecture for at-speed silicon debug based on lossy compression. The proposed architecture enables a new debug methodology that accelerates the identification of the erroneous samples that occur intermittently over a long observation window by avoiding debug experiments that capture only error-free data. The proposed solution is applicable to both automatic test equipment-based debug and in-field debug on application boards, as long as the debug experiments are repeatable and the reference data at the probe signals are deterministically computed using a fast behavioral model of the circuit under debug.

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.