Silicon Carbide Metal-oxide-semiconductor Field-effect Transistors Research Articles

A Programmable Gate Driver Module-Based Multistage Voltage Regulation SiC MOSFET Switching Strategy

Silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs), as a new material, have the advantages of low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency compared with silicon (Si)-based MOSFETs. Therefore, in many industrial applications, Si MOSFETs have been replaced by SiC MOSFETs. However, as the switching speed increases exponentially, some problems are amplified, the most serious of which is the overshoot of current and voltage. The increase in voltage and current slope caused by high switching speeds inevitably leads to overshoot, oscillations, and additional losses in the circuit. This paper focusses on the actual performance of the optimised switching strategy (OSS) in circuit testing and combines the existing simulation results to verify the practicability of OSS. In this paper, the optimised switching strategy is introduced first, and then, the LTspice model of SiC MOSFET is established in detail and verifies the feasibility of the OSS through half-bridge circuit simulation. Finally, the test platform is built using a programmable gate drive module (2ASC-12A1HP). Through a 400 V/30 A double-pulse test, the practicality of the OSS is verified. The experiments show that the OSS can greatly improve the switching performance of SiC MOSFETs.

Development of an inductive energy storage pulsed power supply using SiC semiconductor devices for ozone production by streamer discharges

An inductive energy storage (IES) pulsed power generator driven by a silicon carbide metal oxide semiconductor field effect transistor (SiC-MOSFET) with a blocking voltage of 1.2 kV was developed. The IES pulsed power generator consists of a capacitor, a pulsed transformer and the SiC-MOSFET used as an opening switch. The influence of the turn ratio of the pulsed transformer on the output voltage was evaluated. The output voltage amplitude increased with increasing secondary turn ratio. Under the conditions of no load, a peak output voltage of 13 kV and a pulse width of 120 ns were obtained with a voltage across the drain–source terminals of the MOSFET of 1 kV. The peak voltage increased, and the peak current and pulse width decreased, with increasing load resistance and decreased capacitance. The maximum energy transfer efficiency was obtained at 500 Ω and was approximately 56%.

High-temperature time-dependent dielectric breakdown of 4H-SiC MOS capacitors

—With the rapid applications of silicon carbide metal–oxide–semiconductor field-effect transistor (SiC MOSFET) power devices, further improving the performance of SiC MOSFET device through enhancing its gate oxide reliability is one of the crucial directions. The density of interface states in a SiC MOSFET is a significant parameter that affects the reliability of the gate oxide layer. In this paper, the SiC MOS capacitors (MOSCAPs) were prepared by the 1250 °C dry oxidation and 1350 °C NO annealing process. Then, we analyzed the mechanisms of the breakdown by two group of ramped experiment. And we still evaluated the reliability of oxide layer via the high-temperature time-dependent dielectric breakdown (TDDB) tests on the prepared MOSCAPs, meanwhile, the temperature effect on the reliability was considered. Furthermore, the E, 1/E, and E models with Weibull plotting were used to calculate the tBD lifetimes and failure analysis was carried on the failed samples finally. The results indicate that: (1) the impact of the generation and accumulation of the traps in the oxide, which is the main mechanisms of device failure; (2) The prediction of lifetime was calculated with three models at different acceleration factors; (3) at high-temperature, although the lower the density of interface states is, the Si epitaxial growth and C cluster will manifest in the oxide surface and lead to the breakdown of SiC MOSCAPs.

Collaborative Training of Data-Driven Remaining Useful Life Prediction Models Using Federated Learning

Remaining useful life prediction models are a central aspect of developing modern and capable prognostics and health management systems. Recently, such models are increasingly data-driven and based on various machine learning techniques, in particular deep neural networks. Such models are notoriously “data hungry”, i.e., to get adequate performance of such models, a substantial amount of diverse training data is needed. However, in several domains in which one would like to deploy data-driven remaining useful life models, there is a lack of data or data are distributed among several actors. Often these actors, for various reasons, cannot share data among themselves. In this paper a method for collaborative training of remaining useful life models based on federated learning is presented. In this setting, actors do not need to share locally held secret data, only model updates. Model updates are aggregated by a central server, and subsequently sent back to each of the clients, until convergence. There are numerous strategies for aggregating clients’ model updates and in this paper two strategies will be explored: 1) federated averaging and 2) federated learning with personalization layers. Federated averaging is the common baseline federated learning strategy where the clients’ models are averaged by the central server to update the global model. Federated averaging has been shown to have a limited ability to deal with non-identically and independently distributed data. To mitigate this problem, federated learning with personalization layers, a strategy similar to federated averaging but where each client is allowed to append custom layers to their local model, is explored. The two federated learning strategies will be evaluated on two datasets: 1) run-to-failure trajectories from power cycling of silicon-carbide metal-oxide semiconductor field-effect transistors, and 2) C-MAPSS, a well-known simulated dataset of turbofan jet engines. Two neural network model architectures commonly used in remaining useful life prediction, long short-term memory with multi-layer perceptron feature extractors, and convolutional gated recurrent unit, will be used for the evaluation. It is shown that similar or better performance is achieved when using federated learning compared to when the model is only trained on local data.

Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests

Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

Improved Design of a SiC MOSFET Gate Drive with Crosstalk Suppression Capability

For high-frequency switching applications, silicon carbide (SiC) devices are more suitable than silicon-based devices, which is conducive to improving the efficiency and power density of power electronic equipment. However, as the switching frequency increases, the influence of parasitic parameters on the switching characteristics of devices becomes increasingly apparent. When SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are applied in bridge circuits, the crosstalk problem easily occurs with the complementary conduction of upper and lower transistors, which seriously limits the promotion of SiC MOSFETs. However, the existing crosstalk suppression drive circuit tends to increase the switching loss, switching delay, and control complexity; therefore, a gate drive with crosstalk suppression capability is proposed. In this paper, the gate drive has two features: a negative voltage to shut down the SiC MOSFET; and an adjustment of the gate-source equivalent impedance. To accomplish this goal, the mechanism of crosstalk voltage generation is analyzed. Furthermore, the operation principle of the gate drive is analyzed, and the parameters of the gate drive are designed. Eventually, the proposed gate drive is verified by an LTspice simulation and experimental platform. The results prove that the gate drive can suppress the crosstalk voltage without affecting the switching speed.

Gate driver, snubber and circuit design considerations for fast‐switching series‐connected SiC MOSFETs

AbstractSeries connection of Silicon Carbide (SiC) Metal‐Oxide‐Semiconductor Field‐Effect Transistors (MOSFETs) is an interesting solution to design switches for voltages that are not yet commercially available or limited for single‐die devices. However, inherent static and dynamic voltage balancing must be achieved. Voltage imbalance is caused by the device parameters spread, whose impact is pronounced in low‐inductive circuit layouts. This study investigates the optimal design and tuning limits of resistor‐capacitor (RC)‐snubber circuits and non‐adaptive, standard, voltage‐source gate drivers for achieving the best balancing in transient and steady‐state voltage distributions among series‐connected discrete SiC MOSFETs operating at speeds up to . It has been shown that a larger parameter mismatch will lead to uneven switching energy losses and larger voltage imbalances. It was also experimentally shown that increasing the gate resistor to slow down the devices will not always improve balancing when their parameter spread is large. Thus, tuning recommendations for the RC‐snubber circuit and gate driver were developed based on these findings.

Multi-objective topology optimization design of silicon carbide metal oxide semiconductor field effect transistors power module liquid-cooled heatsink for electric vehicles

Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) is gradually replacing silicon-based insulated gate bipolar transistor (IGBT) as the switching devices in electric vehicle power inverters due to its higher operating temperatures, switching speeds, and frequencyies. However, the high switching frequency of SiC MOSFETs can increase the losses of the power inverter, resulting in an increase in the temperature, which will limit the performance of power inverters. The improvement of power module performance is mainly controlled by optimizing its control methods during operation and improving its cooling system. Currently, the liquid-cooled heatsink used in power modules have disadvantages such as large flow resistance and poor heat dissipation performance. In order to enhance the performance of the heatsink, this study first established a three-dimensional finite element model of SiC MOSFETs power module based on a pin fin heatsink. The accuracy of the model was verified by numerical and experimental methods. Secondly, based on numerical analysis, a multi-objective topology optimization method for the power module liquid-cooled heatsink is proposed. This method takes heat exchange and fluid dissipation energy as the objective function and uses weight factors to adjust the influence of each on the objective functions. Additionally, the temperature distribution of the heatsink is considered to optimize its performance. Finally, the numerical results show that the topology-optimized heatsink exhibits better performance at high coolant volumetric flow rates. When the coolant volumetric flow rate is 14 L/min, the pressure drops of topology-optimized heatsink is reduced by 63.94 % and the junction temperature of the power module is reduced by 0.24 % compared with the pin fin heatsink. This topologically optimized heatsink could be helpful to improve the performance of existing power module heatsinks.

A Brief Review of Single-Event Burnout Failure Mechanisms and Design Tolerances of Silicon Carbide Power MOSFETs

Radiation hardening of power MOSFETs (metal oxide semiconductor field effect transistors) is of the highest priority for sustaining high-power systems in the space radiation environment. Silicon carbide (SiC)-based power electronics are being investigated as a strong alternative for high power spaceborne power electronic systems. SiC MOSFETs have been shown to be most prone to single-event burnout (SEB) from space radiation. The current knowledge of SiC MOSFET device degradation and failure mechanisms are reviewed in this paper. Additionally, the viability of radiation tolerant SiC MOSFET designs and the modeling methods of SEB phenomena are evaluated. A merit system is proposed to consider the performance of radiation tolerance and nominal electrical performance. Criteria needed for high-fidelity SEB simulations are also reviewed. This paper stands as a necessary analytical review to intercede the development of radiation-hardened power devices for space and extreme environment applications.

The Effects of a Gate Bias Condition on 1.2 kV SiC MOSFETs during Irradiating Gamma-Radiation.

We investigated the effects of gate bias regarding the degradation of electrical characteristics during gamma irradiation. Moreover, we observed the punch through failure of 1.2 kV rated commercial Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) due to the influence of gate bias. In addition, the threshold voltage (VT) and on-resistance (Ron) of the SiC MOSFETs decreased significantly by the influence of gate bias during gamma irradiation. We extracted the concentration of carriers and fixed charge (QF) in oxide using N-type SiC MOS capacitors and Transmission Line Measurement (TLM) patterns to analyze the effects of gamma irradiation. The Total Ionizing Dose (TID) effect caused by high-energy gamma-ray irradiation resulted in an increase in the concentration of holes and QF in both SiC and oxide. To analyze the phenomenon for increment of hole concentration in the device under gate bias, we extracted the subthreshold swing of SiC MOSFETs and verified the origin of TID effects accelerated by the gate bias. The QF and doping concentration of p-well values extracted from the experiments were used in TCAD simulations (version 2022.03) of the planar SiC MOSFET. As a result of analyzing the energy band diagram at the channel region of 1.2 kV SiC MOSFETs, it was verified that punch-through can occur in 1.2 kV SiC MOSFETs when the gate bias is applied, as the TID effect is accelerated by the gate bias.

An investigation into the short-circuit characteristics of Sic MOSFET power devices

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) devices exhibit substantial prospects for application under extreme operational conditions, including elevated temperatures, high voltages, and high frequencies. Nevertheless, owing to their distinctive material and structural attributes, SiC MOSFET devices are not devoid of challenges, with the short-circuit phenomenon constituting a pivotal avenue of inquiry. The short-circuit effect pertains to the abrupt escalation of leakage current that these devices might undergo under elevated voltage conditions, thereby exerting a perturbing influence on their stability and reliability. Investigations into the short-circuit effect predominantly revolve around two dimensions: one involves comprehending its underlying physical mechanisms, while the other centers on identifying commensurate remedial approaches.With respect to the underlying physical mechanisms, researchers have discerned that the elevated breakdown field strength and augmented carrier mobility intrinsic to SiC materials engender an augmentation in leakage current, consequently giving rise to the short-circuit effect. Furthermore, factors such as oxide layer anomalies and surface states are also conceivable catalysts for the surge in leakage current. To rectify this predicament, scholars have proffered a panoply of stratagems, encompassing the optimization of material synthesis processes, enhancement of oxide layer quality, refinement of device structural designs, and incorporation of protective circuitry, among others. In summation, the investigation of the short-circuit effect in silicon carbide MOSFET devices is fundamentally aimed at attaining an in-depth comprehension of its causative mechanisms. Moreover, it endeavors to proffer efficacious resolutions conducive to augmenting the reliability and steadfastness of these devices within high-temperature and high-voltage environments, thereby facilitating their widespread integration within the ambit of high-performance power electronics.

Research and analysis of electromagnetic interference of a motor drive control system based on PMSM with SiC MOSFET for new energy electric vehicles

Sustainable development in the 21st century faces significant challenges due to finite reserves of fossil fuels and environmental pollution. In the context of new energy electric vehicles (NEEVs), the wide-bandgap semiconductor known as the silicon carbide–metal oxide–semiconductor field-effect transistor (SiC MOSFET) and the permanent magnet synchronous motor (PMSM) have emerged as advantageous sources. However, the use of these components gives rise to electromagnetic interference (EMI) issues, which impede the achievement of electromagnetic compatibility (EMC) standards in the motor drive control system. This paper aims to elucidate the generation mechanism, propagation path, and test infrastructure of EMI. Furthermore, it proposes a system-level conducted EMI equivalent circuit model for the motor drive control system, encompassing the power battery pack, busbar cable, LISN, three-phase inverter, and PMSM. Building upon this foundation, the principles for suppressing and optimizing EMI noise are discussed. The paper concludes with the validation of simulations and experimental results, which demonstrate the effectiveness of the proposed approach. It is anticipated that professionals with an interest in the field of EMI/EMC will find this paper to be of both theoretical and practical importance.

New SiC Kicker Power Supply for J-PARC

A new kicker power supply using silicon carbide metal–oxide semiconductor field-effect transistors (SiC-MOSFETs) is under development at the Japan Proton Accelerator Research Complex (J-PARC). SiC-MOSFETs fabricate compact high-speed pulse power supplies to replace the thyratron switch power supply. The base circuit of the new power supply uses the linear transformer driver (LTD) system, and the semi-conductor module circuit comprises a radial symmetry type that achieves low noise. The three main components of the current kicker power supply, i.e., the thyratron, pulse-forming network (PFN) circuit, and end clipper, can be assembled on a single board as the new module circuit board. The new power supply contains a 1.25 kV/2 kA main board that forms a trapezoidal pulse and a 0.1 kV/2 kA correction board, compensating for the flat section droop. The 32 main boards and 20 correction boards are hierarchically connected in series to achieve the waveform specifications required for the J-PARC rapid cycling synchrotron (RCS) kicker power supply: output voltage of 40 kV, output current of 2 kA, and pulse width of 1.2 μs. Furthermore, a 25 % power saving has been confirmed and an insulating cylinder for the conductor has been developed to suppress corona discharge and withstand continuous operation for a long time.

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

Low Inductive Characterization of Fast-Switching SiC MOSFETs and Active Gate Driver Units

Accurate switching device characterization is necessary for effectively utilizing the technological ad-vantages of Silicon Carbide (SiC) Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) over their Silicon (Si) Insulated-Gate Bipolar Transistor (IGBT) counterparts. With switching times of few nanoseconds, the unprecedented switching speed of SiC semiconductor devices challenges today's converter and characterization setup designs in regard to parasitic layout inductances for optimal conversion and reliable characterization data. Fur-thermore, active gate driving is a key to unlock the potential of SiC MOSFETs, but requires performance assessment prior to integration. This paper presents a low-inductive test platform for flexible and high-accuracy characterization of fast-switching SiC MOSFETs and active gate drivers evalu-ation. The test circuit delivers high quality characterization data that is comparable with a commercial dynamic power device characterizer. In addition to the conventional hard-switching double-pulse tests with a two-level voltage source gate driver, the test circuit offers soft-switching and gate driver evaluation capability in addition. This test platform is a valuable tool for obtaining reliable characterization data to develop more accurate SiC MOSFET simulation models, and evaluate the combination of gate driver and MOSFET prior to the prototyping phase of a converter.

Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures

To clarify the current research situation and offer a better understanding of the reliability for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs), a comparison among the reliability mechanisms between planar-gate and trench-gate SiC power MOSFETs, which have not been comprehensively summarized, is made in this work. The latest studies focusing on the reliability issues of commercial SiC MOSFET products, including the planar-gate device, the double-trench device and the asymmetric trench-gate device, are reviewed. For the existing of the gate trenches and the unique structures protecting them, SiC trench-gate MOSFETs express quite different instability phenomena from the planar-gate ones under various ultimate and long-term electro-thermal stresses. The influences of these stresses closely related to the practical operation conditions on SiC power MOSFETs, including the avalanche stress, the short-circuit (SC) stress, the surge current stress of the body diode, and the switching stress, are discussed and reviewed in details.

Comparison of Gamma Irradiation Effects on Short Circuit Characteristics of SiC MOSFET Power Devices between Planar and Trench Structures

The short circuit withstand energy (SCWE) variations, and short circuit withstand time (SCWT) variations, of planar and trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices are studied after exposure to a total ionizing dose (TID). The results for ON bias are explored. The SCWE and SCWT are studied for planar and trench SiC MOSFET power devices tested for TID with gamma irradiation. A higher degradation phenomenon for the SCWE and SCWT are observed for the planar SiC MOSFET. The physical mechanisms for these variations are analyzed and confirmed by technology computer-aided design (TCAD) simulation.

Temperature and total ionizing dose effects of SiC MOSFET and their synergistic characteristics

In light of the extreme environmental conditions of temperature and radiation faced by silicon carbide Metal–Oxide-Semiconductor Field-Effect Transistor (SiC MOSFETs) in aerospace electronic systems, the damage characteristics induced by high-temperature stress and Total Ionizing Dose (TID) radiation were compared. Moreover, the synergistic effect of temperature stress and TID on the performance of SiC MOSFETs was studied. The impact of temperature stress and radiation on threshold voltage and static power current is consistent; However, the degradation trend of on-resistance is opposite. The research shows that after temperature stress removal, the change in device performance parameters can be recovered. The total ionizing dose radiation can cause permanent damage to the device; In the environment of temperature stress and radiation, the increase of temperature can weaken or restrain part of radiation damage.

650V Vertical SiC MOSFETs and Diodes with Improved Terrestrial-Neutron Single-Event Burnout

Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm2) such that essentially no failures (0.01 FIT/cm2) are expected at 400V drain-source bias (VDS) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given VDS operation condition, the FIT/cm2 can be decreased by 10 - 100 times, depending on the VDS value. This allows operation at about 75V higher VDS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

On the Frequency Dependence of the Gate Switching Instability in Silicon Carbide MOSFETs

Silicon carbide power metal-oxide semiconductor field-effect transistors (MOSFETs) are suitable for more compact and energy efficient electric power conversion, pushing forward numerous key technologies in emission-free mobility and green power generation. These applications require fast gate switching up to hundreds of kilohertz. Typically, to assure a clear turn-off state of the electron channel, a negative turn-off gate bias is used in conjunction with a positive turn-on gate bias. Recently, several reports have revealed a new and so far unknown degradation mechanism that emerges during such operation conditions in apparently all commercial silicon carbide MOSFETs. As this mechanism arises upon gate switching, the terms gate switching instability (GSI) and gate switching stress (GSS) for the mechanism and the associated stress, respectively, have been introduced.Here, we show that this degradation mechanism does not depend on the used frequency up to at least 2 MHz, but that it is actually related to the cumulative number of switching cycles. For this purpose, we performed measurements at various frequencies comprising ultra-fast in-situ measurements of the threshold voltage and pre- and post-stress characterization by impedance analysis. The results are important both for understanding the underlying physics and for developing a correct methodology for industrial device qualification.