Silicon-based Integrated Circuit Research Articles

Performance comparison and analysis of silicon-based and carbon-based integrated circuits under VLSI

Since 1960, the semiconductor industry has invented Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Complementary Metal Oxide Semiconductor (CMOS) technologies. Subsequently, the semiconductor-based integrated circuit industry has led a new generation of information revolution, driving the rapid development of various electronic circuit technologies worldwide. With the physical limitations of the silicon semiconductor process, Moores Law is also approaching its physical limit. In the search for new semiconductor materials, carbon nanotube semiconductors have become one of the candidate materials for new semiconductor materials due to their many advantages, and their many characteristic parameters are even better than those of silicon semiconductors of the same size. This article introduces the research status, performance characteristics, and comparison of silicon-based and carbon-based integrated circuits, as well as the current application scenarios of silicon-based and carbon-based integrated circuits in the industry, and the many problems encountered. Finally, this article analyses the future development direction of the integrated circuit industry and the possible challenges it may face.

Demonstration of a Bosonic Quantum Classifier with Data Reuploading.

In a single qubit system, a universal quantum classifier can be realized using the data reuploading technique. In this study, we propose a new quantum classifier applying this technique to bosonic systems and successfully demonstrate it using a silicon-based photonic integrated circuit. We established a theory of quantum machine learning algorithm applicable to bosonic systems and implemented a programmable optical circuit combined with an interferometer. Learning and classification using part of the implemented optical quantum circuit with uncorrelated two photons resulted in a classification with a success probability of 94±0.8% in the proof of principle experiment. As this method can be applied to an arbitrary two-mode N-photon system, further development of optical quantum classifiers, such as extensions to quantum entangled and multiphoton states, is expected in the future.

A W-Band Digitally Controlled Bidirectional Transmission Line Phase Shifter in 22-nm FDSOI

In this letter, a passive bidirectional integrated tunable transmission line (TL) phase shifter (PS) is proposed and demonstrated in the W-band (75–110 GHz). The PS is based on a modified coplanar waveguide (CPW) structure with a conditional meandering ground return path located below the coplanar metal layer on the ground wall. The modified CPW structure achieves a wide phase shift tuning range with a compact PS unit cell A 5-bit digitally controllable PS based on the proposed topology is implemented in the 22-nm fully depleted silicon-on-insulator (FDSOI) process. The PS achieves a worst case phase resolution and loss of 4.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> and 11.5 Db, respectively, in the W-band for a total phase shift of up to 115 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> . To the authors’ knowledge, this represents the highest frequency range for a constant length integrated tunable TL PS in a silicon-based integrated circuit (IC) technology.

Extended-SWIR GeSn LEDs with Reduced Footprint and Efficient Operation Power

Complementary metal oxide semiconductor-compatible short- and midwave infrared emitters are highly coveted for the monolithic integration of silicon-based photonic and electronic integrated circuits to serve a myriad of applications in sensing and communication. In this regard, the group IV germanium–tin (GeSn) material epitaxially grown on silicon (Si) emerges as a promising platform to implement tunable infrared light emitters. Indeed, upon increasing the Sn content, the bandgap of GeSn narrows and becomes direct, making this material system suitable for developing an efficient silicon-compatible emitter. With this perspective, microbridge PIN GeSn LEDs with a small footprint of 1520 μm2 are demonstrated, and their operation performance is investigated. The spectral analysis of the electroluminescence emission exhibits a peak at 2.31 μm, and it red-shifts slightly as the driving current increases. It is found that the microbridge LED operates at a dissipated power as low as 10.8 W at room temperature and just 3 W at 80 K. This demonstrated low operation power is comparable to that reported for LEDs having a significantly larger footprint reaching 106 μm2. The efficient thermal dissipation of the current design helped reduce the heat-induced optical losses, thus enhancing light emission. Further performance improvements are envisioned through thermal and optical simulations of the microbridge design. These simulations indicate that the use of GeSn-on-insulator substrate for developing a similar microbridge device is expected to improve the optical confinement toward the realization of electrically driven GeSn lasers.

2D Bi2O2Se: An Emerging Material Platform for the Next-Generation Electronic Industry

ConspectusSilicon has been the dominant semiconductor for the microelectronics industry since the late 1950s. Following Moore’s law, silicon-based integrated circuit (IC) technology evolved into a 5 nm node by the end of 2020. However, silicon-based electronics face various challenges such as reduced carrier mobility and increased short-channel effects at sub-10 nm nodes. To overcome these drawbacks, two-dimensional (2D) semiconductors are among the most competitive candidate materials for next-generation electronics, due to their intrinsic atomic thickness, flexibility, and dangling-bond-free surfaces. Among all the 2D semiconductors, an air-stable and high-mobility 2D Bi2O2Se semiconductor, a novel ternary material, has some prominent advantages that make it particularly favorable in the electronics industry. First, it demonstrates ultrahigh carrier mobility, moderate band gap, outstanding stability, and excellent mechanical properties. Second, it can react with oxygen plasma or oxygen at elevated temperatures to form a high-κ native oxide Bi2SeO5. The native oxide Bi2SeO5 forms an atomically sharp interface with Bi2O2Se and can directly serve as a gate dielectric. Bi2O2Se is also embodied with some interesting physical properties such as strong spin–orbit coupling, dimerized selenium vacancies, and ferroelectricity. Taking advantage of these properties, researchers have fabricated high-performance electronic devices, including logic devices, optoelectronics, thermoelectrics, sensors, and memory devices.In this account, we will systematically review the structure of 2D Bi2O2Se, including its crystal structure, surface structure, point defects, and electronic band structure and how these structures can affect the electron transport in 2D Bi2O2Se. We will then discuss different approaches to synthesize this material including chemical vapor deposition (CVD), metal–organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and the solution-assisted method. All these methods show great potential in large-scale production. Third, we will discuss how the structure of Bi2O2Se affects its chemical and physical properties such as chemical reactivity and ferroelectric, piezoelectric, and electromechanical properties. Fourth, we will talk about how to make use of these properties in electronic devices, including field-effect transistors, logic gates, bolometers, photodetectors, thermoelectrics, piezoelectrics, sensors, and memory devices. Finally, we will put forward our idea on how to pattern large-area Bi2O2Se thin films into isolated channel regions and integrate these devices together into full-functioning circuits. We believe that 2D Bi2O2Se is a promising semiconductor, as a great diversity of high-performance 2D Bi2O2Se-based devices have demonstrated. Hopefully, the unique characteristics of 2D Bi2O2Se can provide additional opportunities to complement or replace silicon as the material platform of the next-generation electronics industry. To fill the gap between dreams and reality, there is still much work to be done, especially in large-scale material synthesis and systematic device integration.

Nonreciprocal emergence of hybridized magnons in magnetic thin films

Magnons (the quanta of spin waves), unlike electrons, do not suffer from Ohmic losses, which makes them an attractive information carrier in communication and data processing. The possibility of nonreciprocal magnon propagation is of great practical relevance to directional communications, particularly when the nonreciprocity is steerable through magnons themselves in a monologic magnonic device. This work demonstrates explicitly such nonreciprocity in the mode profiles of magnons in ${\mathrm{Ni}}_{79}{\mathrm{Fe}}_{21}$ thin films. Evidence of nonreciprocal emergence of hybridized dipole-exchange spin waves at two surfaces of ${\mathrm{Ni}}_{79}{\mathrm{Fe}}_{21}$ nanofilms deposited on a surface oxide silicon substrate is provided by studying magnon transmission and asymmetry via Brillouin light scattering measurements. The dipole-dominated spin wave and exchange-dominated spin wave are found to be localized near the top and bottom surfaces, respectively, and travel along opposite directions. The nonreciprocity and the localization can be tuned by an in-plane magnetic field. Our findings provide a simple and flexible approach to nonreciprocal all-magnon logic devices highly compatible with silicon-based integrated circuit technology.

A 4–32 GHz SiGe Multi-Octave Power Amplifier With 20 dBm Peak Power, 18.6 dB Peak Gain and 156% Power Fractional Bandwidth

This letter presents the design and characterization results of a multi-octave power amplifier (MOPA) fabricated in a 0.13- $\mu \text{m}$ SiGe-BiCMOS technology. The single-stage power amplifier is implemented as the stack of a cascode amplifier combining broadband input matching network with resistive feedback, and a common-base amplifier with base capacitive feedback. Measurement results show that the design delivers a peak saturated output power level of 20.2 dBm, with output of 1 dB compression at 19.4 dBm. The measured 3-dB power bandwidth is from 4 to 32 GHz, covering three octaves. The corresponding power fractional bandwidth (PFBW) is 156%. The measured peak power added efficiency is 20.6%, and peak small-signal gain is 18.6 dB. The fabricated integrated circuit occupies an area of 0.71 mm2. To compare state-of-the-art MOPAs, the power amplifier figure of merit defined by the international technology roadmap for semiconductors (ITRS) is modified to include PFBW and area. To the best of authors’ knowledge, the presented design achieves the highest figure of merit among multi-octave PAs in a silicon-based integrated circuit technology reported in the literature.

Analytic model of spalling technique for thickness-controlled separation of single-crystalline semiconductor layers

Thickness-controlled separation of a thin layer of single-crystalline semiconductors from its bulk substrate has been developed for the co-integration of compound semiconductors with silicon-based integrated circuit chips and the fabrication of high-performance flexible devices. Recently, a controlled spalling technique that can mechanically separate single-crystalline semiconductor layers has been actively demonstrated because of the process simplicity and the less limitation on the use of materials. Here, we developed an analytic model that can precisely estimate the spalling depth. In this model, the spalling depth was calculated from the thermodynamic equilibrium condition in which total strain energy accumulated in a separated layer is balanced with the crystal binding energy. We experimentally investigated the dependence of the spalling depth on the stressor layer thickness and stress, and we compared the empirical results with the proposed analytic model. We also verified that the crack initiation angle of the spalling process is determined by the binding energy contrast in the main crystal orientations in the semiconductor.

Mitigation of speckle noise in laser Doppler vibrometry by using a scanning average method.

We present a scanning average method used in laser Doppler vibrometry systems for mitigating the noise induced by dynamic speckles. In this method, the measurement beam is scanned over the target surface within the area of interest at a relatively high frequency. Then an averaging operation (e.g., low-pass filtering) is applied to the acquired photocurrent signals to remove the impacts of the scan. Movement signals recovered from the averaged photocurrents turn out to have lower speckle-induced noise. We report the experimental demonstration of this technique through the use of a silicon-based photonic integrated circuit.

Control of Crystallinity in PbPc:C60 Blend Film and Application for Inverted Near-Infrared Organic Photodetector.

Inverted near-infrared (NIR) organic photodetectors (OPDs) are required to combine the OPDs with an n-channel silicon-based integrated circuit. NIR absorption in the 930-960 nm range is important because the intensity of solar irradiation is low in this wavelength regime. Here, we controlled the crystallinity of lead(II) phthalocyanine (PbPc) in a PbPc:C60 blendfilmto obtain NIR absorption. To form a triclinic phase responsible for NIR light absorption, a substrate was heated during fabrication and C60 was used as a templating layer, as well as an electron extraction layer, for an inverted structure. NIR absorption near 950 nm was enhanced, and the structural properties of the film changed dramatically. The OPD with enhanced NIR absorption exhibited a responsivity of 244 mA/W and an external quantum efficiency of 31.1% at a reverse bias of -3 V and 970 nm. The OPD detectivity also increased to 9.01 × 1012 and 1.36 × 1011 cm Hz1/2/W under a zero bias and a reverse bias of -3 V, respectively.

Light emission from a poly-silicon device with carrier injection engineering

Development work was conducted on N+PN+PN+ Poly silicon light-emitting devices which are compatible with silicon-based integrated circuit technology. We discuss the emission characteristics of visible light by a monolithically integrated Poly-Si diode under reverse bias. With the structure of modified PN junctions, the carriers injection occurs through silicon slabs of only a few nanometer thick. The dominant role of non-radiative recombination at the N+ and P+ contacts is diminished by confining the injected carriers around the PN junction’s interface in which avalanche takes place. The current-dependent optical radiation presents a broad spectrum in the 400- to 900-nm range. Although the emission efficiency is low due to silicon’s indirect bandgap, it is advantageous to utilize these devices in all-silicon optoelectronic integrated circuits (OIC’s).

The chemical states and atomic structure evolution of ultralow-energy high-dose Boron implanted Si(110) via laser annealing

Further scale down the dimension of silicon-based integrated circuit is a crucial trend in semiconductor fabrication. One of the most critical issues in the nano-device fabrication is to confirm the atomic structure evolution of the ultrathin shallow junction. In this report, UV Raman spectroscopy, X-ray photoelectron spectroscopy (XPS), X-ray absorption near edge structure (XANES) and reflective second harmonic generation (RSHG) are utilized to monitor the pulse laser induced atomic structure evolution of ultralow-energy high-dose Boron implanted Si(110) at room and cold substrate temperature. A peak feature around 480 cm−1 resolved in UV Raman spectra indicates the formation of Si-B bond after the laser irradiation. The red shift of binding energy of Si element (~99 eV) in XPS and the evolution of absorption peak (~196.2 eV) in XANES reveal that the changes in the chemical states of ultra shallow junction strongly correlate to the activation process of Boron implantation, which is confirmed by RSHG measurement. The substrate temperature effect in the recrystallization of Boron implanted region is also realized by cross-section high-resolution TEM (HRTEM). The phenomena of Si-B bond formation and ultra-shallow junction recrystallization can be traced and applied to improve the reliability of Si ultra shallow junction in the future.

Thermoelectrical modelling and simulation of devices based on VO2

Limits of development of conventional silicon-based integrated circuits get closer. More and more effort is done to develop new devices for integrated circuits. A promising structure is based on the semiconductor-to-metal phase change of vanadium-dioxide at about 67°C. In these circuits the information is carried by combined thermal and electrical currents. For device modelling and circuit design, accurate distributed electro-thermal transient simulation is mandatory. This paper is the first one to present an electro-thermal transient simulation method for VO2 devices operating in real-world conditions. The paper presents three VO2 material models, the algorithmic extension of an electro-thermal field simulator to be able to handle hysteresis and the transient simulation issues of VO2 and the modelling of VO2 based devices. The paper compares measured and simulated device characteristics.

A room-temperature-operated Si LED with β-FeSi2 nanocrystals in the active layer: μW emission power at 1.5 μm

This article describes the development of an Si-based light-emitting diode with β-FeSi2 nanocrystals embedded in the active layer. Favorable epitaxial conditions allow us to obtain a direct band gap type-I band alignment Si/β-FeSi2 nanocrystals/Si heterostructure with optical transition at a wavelength range of 1500–1550 nm at room temperature. Transmission electron microscopy data reveal strained, defect-free β-FeSi2 nanocrystals of diameter 6 and 25 nm embedded in the Si matrix. Intense electroluminescence was observed at a pumping current density as low as 0.7 A/cm2. The device reached an optical emission power of up to 25 μW at 9 A/cm2 with an external quantum efficiency of 0.009%. Watt–Ampere characteristic linearity suggests that the optical power margin of the light-emitting diode has not been exhausted. Band structure calculations explain the luminescence as being mainly due to radiative recombination in the large β-FeSi2 nanocrystals resulting from the realization of an indirect-to-direct band gap electronic configuration transformation arising from a favorable deformation of nanocrystals. The direct band gap structure and the measured short decay time of the luminescence of several tens of ns give rise to a fast operation speed for the device. Thus a method for developing a silicon-based photonic integrated circuit, combining complementary metal-oxide-semiconductor technology functionality and near-infrared light emission, is reported here.

(Invited) SiGe BiCMOS for Optoelectronics

Silicon-based electronic-photonic integrated circuit (ePIC) technology enables a high degree of integration of optoelectronic sub-systems for optical communications. There are basically two approaches for merging photonics with electronics, hybrid assembly or monolithic integration. In hybrid integration approaches, electronic-only chips are combined with photonic-only chips after their separate fabrication [1]. Advantage is here that a mutual interference of photonic and electronic device fabrication can easily be avoided which is a more difficult task for most monolithic integration approaches. On the other hand, monolithic integration of photonic devices such as detectors and modulators in the frontend-of-line (FEOL) of a Si-based integrated circuit technology allows for shortest possible interconnects between photonics and electronics from which high-speed performance of electronic-photonic integrated circuits can greatly benefit. Moreover, monolithic electronic-photonic integration leads to shrinking form-factors and reduced assembly. Monolithic integration of Si photonics has been pursued for some time, chiefly on base of CMOS technologies [2, 3]. Looking beyond 100G systems, baud-rates exceeding 50GBd are needed for 400G transceivers, requiring very fast driving electronics. High-speed transistors are therefore a prerequisite for high-performance ePIC technology. Already today, SiGe bipolar or BiCMOS technologies are frequently deployed for broadband applications in high-speed discrete photonics. A key device figure of merit is the product of transit frequency and breakdown voltage (fT × BV) in which state-of-the-art SiGe heterojunction bipolar transistors (HBTs) outperform scaled MOS transistors. In result, SiGe HBTs are often preferred over CMOS for high-speed analog circuits. Although waveguide-based optics leads to lower form-factors compared to discrete solutions, there are limits to downsizing of integrated photonic devices because of the wavelength of light and the available index contrast. This puts constraints on the reduction of voltage swing required to drive photonic devices such as modulators. In practice, the required voltage swing remains comparable to discrete solutions. On the other hand, complex real-time mixed signal systems requiring large digital cores are typically implemented in highly scaled CMOS technologies that provide only a limited output voltage swing. Integrating Si photonics with SiGe HBT technology is therefore an excellent match for high-speed A/D or D/A interfaces. SiGe-HBT-based ePIC technology enables direct driving of integrated photonic devices by high-speed digital electronics such as advanced signal processing. Here, we will give an overview about IHP’s work in ePIC technology development under use of different SiGe BiCMOS baseline processes. Main focus is on “Photonic BiCMOS”, a new monolithic ePIC technology which combines high-performance BiCMOS technology with high-speed photonic devices for electronic-photonic sub-modules for next generation communication networks. We will describe the main features of this technology, including an overview of offered photonic and electronic devices. Examples of demonstrator circuits fabricated in a first generation of the new technology, comprising 200GHz SiGe HBTs and 30GHz Ge photodiodes, are also presented. Among these circuits are a 40Gbps monolithically integrated linear receiver [4] and a monolithically integrated segmented driver and Mach-Zehnder modulator with 13 dB extinction ratio at 28 Gbps [5]. We will also present our work to integrate a new Ge photodiode with 70GHz bandwidth and to improve the bipolar transistor performance to enable the fabrication of integrated receivers and transmitters with strongly increased optical line rates [6, 7]. In a second part of the talk we will demonstrate the potential of SiGe BiCMOS as the ‘electronics supplier’ for the hybrid integration approach, using IHP’s 0.13µm BiCMOS process SG13S offering HBTs with 240/320GHz fT/fmax. [1] F. Boeuf et al., “A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s Applications,” in 2013 IEEE International Electron Devices Meeting (IEDM), pp. 353-356 [2] S. Assefa et al., “A 90nm CMOS integrated nano-photonics technology for 25Gbps WDM optical communications applications,” in 2012 IEEE International Electron Devices Meeting (IEDM), pp. 809-811 [3] R. Meade et al., “Integration of silicon photonics in bulk CMOS,” 2014 Symposium on VLSI Technology Digest of Technical Papers, DOI:10.1109/VLSIT.2014.6894427 [4] A. Awny et al., “A 40Gb/s monolithically integrated linear photonic receiver in a 0.25μm BiCMOS SiGe:C Technology,” IEEE Microwave and Wireless Components Letters, 25 (2015), 7, 469-471 [5] P. Rito et al., “A Monolithically Integrated Segmented Driver and Modulator in 0.25 μm SiGe:C BiCMOS with 13 dB Extinction Ratio at 28 Gb/s,” in press [6] D. Knoll et al., “High-performance photonic BiCMOS Process for the fabrication of high-bandwidth electronic-photonic integrated circuits,” in 2015 IEEE International Electron Devices Meeting (IEDM), pp. 402-405 [7] S. Lischke et al., “Photonic BiCMOS technology – Enabler for Si-based, monolithically integrated transceivers towards 400 G,” in press

(Invited) SiGe BiCMOS for Optoelectronics

Silicon-based electronic-photonic integrated circuit (ePIC) technology enables a high degree of integration of optoelectronic subsystems for optical communications. In this paper we give an overview about IHP’s work in ePIC technology development under use of different SiGe BiCMOS baseline processes. Focus is on "Photonic BiCMOS", a new monolithic ePIC technology which combines high-performance BiCMOS technology with high-speed photonic devices for electronic-photonic submodules for next generation communication networks. Main features of this technology are described, including an overview of offered photonic and electronic devices. Examples of demonstrator circuits fabricated in the new technology are also presented. Another approach of merging photonics with electronics is hybrid assembly. In a second part of the paper we will demonstrate the potential of SiGe BiCMOS as the ‘electronics supplier’ for this approach.

Advanced Integration Techniques on Broadband Millimeter-Wave Beam Steering for 5G Wireless Networks and Beyond

Recently, the desired very high throughput of 5G wireless networks drives millimeter-wave (mm-wave) communication into practical applications. A phased array technique is required to increase the effective antenna aperture at mm-wave frequency. Integrated solutions of beamforming/beam steering are extremely attractive for practical implementations. After a discussion on the basic principles of radio beam steering, we review and explore the recent advanced integration techniques of silicon-based electronic integrated circuits (EICs), photonic integrated circuits (PICs), and antenna-on-chip (AoC). For EIC, the latest advanced designs of on-chip true time delay (TTD) are explored. Even with such advances, the fundamental loss of a silicon-based EIC still exists, which can be solved by advanced PIC solutions with ultra-broad bandwidth and low loss. Advanced PIC designs for mm-wave beam steering are then reviewed with emphasis on an optical TTD. Different from the mature silicon-based EIC, the photonic integration technology for PIC is still under development. In this paper, we review and explore the potential photonic integration platforms and discuss how a monolithic integration based on photonic membranes fits the photonic mm-wave beam steering application, especially for the ease of EIC and PIC integration on a single chip. To combine EIC, for its accurate and mature fabrication techniques, with PIC, for its ultra-broad bandwidth and low loss, a hierarchical mm-wave beam steering chip with large-array delays realized in PIC and sub-array delays realized in EIC can be a future-proof solution. Moreover, the antenna units can be further integrated on such a chip using AoC techniques. Among the mentioned techniques, the integration trends on device and system levels are discussed extensively.

An all-silicon single-photon source by unconventional photon blockade

The lack of suitable quantum emitters in silicon and silicon-based materials has prevented the realization of room temperature, compact, stable, and integrated sources of single photons in a scalable on-chip architecture, so far. Current approaches rely on exploiting the enhanced optical nonlinearity of silicon through light confinement or slow-light propagation, and are based on parametric processes that typically require substantial input energy and spatial footprint to reach a reasonable output yield. Here we propose an alternative all-silicon device that employs a different paradigm, namely the interplay between quantum interference and the third-order intrinsic nonlinearity in a system of two coupled optical cavities. This unconventional photon blockade allows to produce antibunched radiation at extremely low input powers. We demonstrate a reliable protocol to operate this mechanism under pulsed optical excitation, as required for device applications, thus implementing a true single-photon source. We finally propose a state-of-art implementation in a standard silicon-based photonic crystal integrated circuit that outperforms existing parametric devices either in input power or footprint area.

Silicon-Based Photonic Integration Beyond the Telecommunication Wavelength Range

In this paper we discuss silicon-based photonic integrated circuit technology for applications beyond the telecommunication wavelength range. Silicon-on-insulator and germanium-on-silicon passive waveguide circuits are described, as well as the integration of III-V semiconductors, IV-VI colloidal nanoparticles and GeSn alloys on these circuits for increasing the functionality. The strong nonlinearity of silicon combined with the low nonlinear absorption in the mid-infrared is exploited to generate picosecond pulse based supercontinuum sources, optical parametric oscillators and wavelength translators connecting the telecommunication wavelength range and the mid-infrared.

Electromigration in Passivated Gold Interconnects for GaAs Devices

Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature.Electromigration lifetimes of large quantities of passivated electroplated Au interconnects were measured utilizing high resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures.A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 µm. All Au lifetime distributions followed log-normal distributions and Black’s model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.