Silicon-based Complementary Metal Oxide Semiconductor Research Articles

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

Investigating the physical mechanism of ion-slicing in AlN and hetero-integrating AlN thin film on Si(100) substrate

Heterogeneously integrating the monocrystal AlN thin films on Si(100) substrates by ion-slicing technique provides a promising high-quality material platform to achieve the monolithic integration of Silicon-based CMOS (Complementary Metal Oxide Semiconductor) and high-performance III-nitride devices. Single crystalline AlN bulk materials implanted by hydrogen ions (H+) were used to elucidate the physical mechanism of the blistering formation in hydrogen implanted AlN with different annealing process. XTEM characterization was performed to reveal the formation of H-induced microcracks which eventually leads to the layer splitting. Using the ion-slicing technique, the AlN thin films were capitally transferred to Si(100) substrate. The crystal quality and the microstructure of the transferred AlN thin film were characterized thoroughly, indicating its exceptional crystal quality with the full width at half maximum (FWHM) for (002) XRC as low as 93.6 arcsec.

Te doping effects on the ferromagnetic performance of the MnGe/Si quantum dots grown by ion beam sputtering deposition

Dilute magnetic MnGe quantum dots (QDs) have been a popular research topic due to their great potential application on spintronics and their natural compatibility with today's highly developed silicon-based complementary metal oxide semiconductor (CMOS) technology. However, the relatively low Curie temperature impedes their ability to maintain the ferromagnetic phase and creates difficulty for their practical application in spintronics at room temperature. Here, we report the first preparation of the Te-doped dilute-magnetic Mn0.064Ge0.895Te0.041/Si QDs by using the ion beam composite target sputtering technique. Growth temperature and deposition thickness dependent QDs density and magnetic properties were investigated systematically. The experimental results indicate that the QD density of Mn0.064Ge0.895Te0.041/Si sample increases first and then reduces with the deposited thickness, while the QDs' diameters increase monotonously from 10.18 ± 0.21–33.6 ± 0.34 nm. Curie temperature of 369 K observed in Mn0.064Ge0.895Te0.041 QDs is higher than that of 295 K observed in Mn0.061Ge0.939 counterparts grown at the same conditions. Correspondingly, the saturation and residual magnetization in the former are much higher than in the latter. The ferromagnetic enhancement can be attributed to that the nonpolar Mn0.064Ge0.936 QDs transform into Rashba polar Mn0.064Ge0.895Te0.041 QDs with the doping of Te ions, which obviously promotes the exchange coupling between holes and Mn atoms. Our work provides a practical approach for improving the ferromagnetism and Curie temperature of silicon-based diluted magnetic semiconductor QDs.

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.

Wafer-Scale Fabrication of CMOS-Compatible Trapping-Mode Infrared Imagers with Colloidal Quantum Dots

Silicon-based complementary metal oxide semiconductor (CMOS) devices have dominated the technological revolution in the past decades. With increasing demands in machine vision, autonomous driving, and artificial intelligence, silicon CMOS imagers, as the major optical information input devices, face great challenges in spectral sensing ranges. In this paper, we demonstrate the development of CMOS-compatible infrared colloidal quantum-dot (CQD) imagers in the broadband short-wave and mid-wave infrared ranges (SWIR and MWIR, 1.5–5 μm). A new device architecture of trapping-mode detectors is proposed, fabricated, and demonstrated with lowered darkcurrents and improved responsivity. The CMOS-compatible fabrication process is completed with two-step sequential spin-coating processes of intrinsic and doped HgTe CQDs on an 8 in. CMOS readout wafer with photoresponse non-uniformity (PRNU) down to 4%, dead pixel rate of 0%, external quantum efficiency up to 175%, and detectivity as high as 2 × 1011 Jones for extended SWIR at 300 K and 8 × 1010 Jones for MWIR at 80 K. Both SWIR images and MWIR thermal images are demonstrated with great potential for semiconductor inspection, chemical identification, and temperature monitoring.

Infrared metasurface absorber based on silicon-based CMOS process.

Metasurface with metal-insulator-metal (MIM) structure has absorption properties for incident light at specific wavelengths. In this paper, we propose an infrared metasurface absorber based on silicon-based complementary metal oxide semiconductor (CMOS) process. By adding the prepared infrared metasurface absorber to the liquid crystal on silicon (LCoS) chip, it is used as the absorbing layer of LCoS configured between the pixel unit and the CMOS driver circuit. The effect of zero-order light caused by the gap between pixels in LCoS spatial light modulator (LCoS-SLM) on the light modulation function of the device is effectively reduced. Experiments show that the LCoS-SLM with infrared metasurface absorption structure can eliminate the zero-order light interference between the pixel gaps to a great extent and improve the modulation efficiency of the device. The proposed LCoS-SLM integrating infrared metasurface absorber structure based on silicon-based CMOS process has the advantages of low-cost and high modulation efficiency, which has high application value in the fields of holographic display, optical computing and optical communication.

Ultrahigh Photogain Short-Wave Infrared Detectors Enabled by Integrating Graphene and Hyperdoped Silicon.

Highly sensitive short-wave infrared (SWIR) detectors, compatible with the silicon-based complementary metal oxide semiconductor (CMOS) process, are regarded as the key enabling components in the miniaturized system for weak signal detection. To date, the high photogain devices are greatly limited by a large bias voltage, low-temperature refrigeration, narrow response band, and complex fabrication processes. Here, we demonstrate high photogain detectors working in the SWIR region at room temperature, which use graphene for charge transport and Te-hyperdoped silicon (Te-Si) for infrared absorption. The prolonged lifetime of carriers, combined with the built-in potential generated at the interface between the graphene and the Te-Si, leads to an ultrahigh photogain of 109 at room temperature (300 K) for 1.55 μm light. The gain can be improved to 1012, accompanied by a noise equivalent power (NEP) of 0.08 pW Hz-1/2 at 80 K. Moreover, the proposed device exhibits a NEP of 4.36 pW Hz-1/2 at 300 K at the wavelength of 2.7 μm, which is exceeding the working region of InGaAs detectors. This research shows that graphene can be used as an efficient platform for silicon-based SWIR detection and provides a strategy for the low-power, uncooled, high-gain infrared detectors compatible with the CMOS process.

A Polarization-Switching, Charge-Trapping, Modulated Arithmetic Logic Unit for In-Memory Computing Based on Ferroelectric Fin Field-Effect Transistors.

Nonvolatile logic devices are crucial for the development of logic-in-memory (LiM) technology to build the next-generation non-von Neumann computing architecture. Ferroelectric field-effect transistors (Fe FET) are one of the most promising candidates for LiMs because of high compatibility with mainstream silicon-based complementary metal-oxide semiconductor processes, nonvolatile memory, and low power consumption. However, because of the unipolar characteristics of a Fe FET, a nonlinear XOR or XNOR logic gate function is difficult to realize with a single device. In addition, because single Fe polarization switch modulation is available in the devices, a reconfigurable logic gate usually needs multiple devices to construct and realize fewer logic functions. Here, we introduced polarization-switching (PS) and charge-trapping (CT) effects in a single Fe FET and fabricated a multi-field-effect transistor with bipolar-like characteristics based on advanced 10 nm node fin field-effect transistors (PS-CT FinFET) with 9 nm thick Hf0.5Zr0.5O2 films. The special hybrid effects of charge-trapping and polarization-switching enabled eight Boolean logic functions with a single PS-CT FinFET and 16 Boolean logic functions with two complementary PS-CT FinFETs were obtained with three operations. Furthermore, reconfigurable full 1 bit adder and subtractor functions were demonstrated by connecting only two n-type and two p-type PS-CT FinFET devices, indicating that the technology was promising for LiM applications.

A Review of Graphene Nanoribbon Field-Effect Transistor Structures

The ascending trend of Moore’s law has stretched to the horizon, where the prospects of carbon-based materials show the potential of replacing the silicon-based complementary metal-oxide semiconductor technology. These alternatives include nanowire transistors, carbon nanotube field-effect transistors, quantum-dot cellular automata, and graphene nanoribbon field-effect transistors (GNRFETs). This paper presents a review of the evolution of graphene, its fabrication process, and graphene-based field-effect transistor device structures. The diverse features of graphene as a material are derived from its structural, electronic, and thermal properties. A brief review of the techniques utilized for the fabrication of GNRFETs is mentioned in this paper. GNRFETs are based on excellent electrical properties that include strong ballistic transport, high current ratio, better compatibility with high K dielectrics, high electron mobility, reliability, scalability, and transconductance. GNRFET structures are reviewed for several aspects which include the Ion/Ioff ratio, subthreshold swing, oxide thickness, high K dielectrics, etc. that help to monitor the improvement in the performance of GNRFET devices. A comparison of the structures is presented to help researchers have a fair idea of the impact of modifications on device performance. The compact model used to simulate GNRFET-based devices is also included in this paper. GNRFET-based devices have several applications to offer in the current scenario. This paper also reports several applications of present GNRFET-based devices.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits.

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Integration of Single Oriented Oxide Superlattices on Silicon Using Various Template Techniques.

To benefit from the diverse functionalities of perovskite oxides in silicon-based complementary metal oxide semiconductor (CMOS) technology, integrating oxides into a silicon platform has become one of the major tasks for oxide research. Using the deposition of LaMnO3/SrTiO3 (STO) superlattices (SLs) as a case study, we demonstrate that (001) single oriented oxide SLs can be integrated on Si using various template techniques, including a single-layer buffer of STO prepared by molecular beam epitaxy (MBE) and pulsed laser deposition, a multilayer buffer of Y-stabilized zirconia/CeO2/LaNiO3/STO, and STO-coated two-dimensional nanosheets of Ca2Nb3O10 (CNO) and reduced graphene oxide. The textured SL grown on STO-coated CNO nanosheets shows the highest crystallinity, owing to the small lattice mismatch between CNO and STO as well as less clamping from a Si substrate. The epitaxial SL grown on STO buffer prepared by MBE suffers the largest thermal strain, giving rise to a strongly suppressed saturation magnetization but an enhanced coercive field, as compared to the reference SL grown on an STO single crystal. These optional template techniques used for integrating oxides on Si are of significance to fulfill practical applications of oxide films in different fields.

New Radiation-Hardened Design of a CMOS Instrumentation Amplifier and its Tolerant Characteristic Analysis

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

Artificial 2D van der Waals Synapse Devices via Interfacial Engineering for Neuromorphic Systems.

Despite extensive investigations of a wide variety of artificial synapse devices aimed at realizing a neuromorphic hardware system, the identification of a physical parameter that modulates synaptic plasticity is still required. In this context, a novel two-dimensional architecture consisting of a NbSe2/WSe2/Nb2O5 heterostructure placed on an SiO2/p+ Si substrate was designed to overcome the limitations of the conventional silicon-based complementary metal-oxide semiconductor technology. NbSe2, WSe2, and Nb2O5 were used as the metal electrode, active channel, and conductance-modulating layer, respectively. Interestingly, it was found that the post-synaptic current was successfully modulated by the thickness of the interlayer Nb2O5, with a thicker interlayer inducing a higher synapse spike current and a stronger interaction in the sequential pulse mode. Introduction of the Nb2O5 interlayer can facilitate the realization of reliable and controllable synaptic devices for brain-inspired integrated neuromorphic systems.

Characterization and analysis of low-noise GaN-HEMT based inverter circuits

In this work, the authors have propounded a novel Gallium Nitride High Electron Mobility Transistor (GaN-HEMT) structure and have analyzed its DC, RF and noise performance parameters. The DC characteristics reveal a high ON-state current in the order of 10−2 A/mm complemented by a near ideal sub-threshold swing of 70 mV/decade. High values of cut-off frequency (ft = 126 GHz) and maximum oscillation frequency (fmax = 224 GHz) are obtained which indicate high frequency range of operation. A minimum noise figure in the order of 10−5 dB has been achieved for lower frequencies of operation that remains considerably low even beyond 30 GHz (1.7 dB at 45 GHz and 4 dB at 100 GHz), indicating low-noise performance at practical operational frequencies. Further, a resistive load inverter based on GaN-HEMT has been proposed to supplant existing Silicon-based Complementary Metal Oxide Semiconductor (CMOS) technology which suffers from extensive scaling limitations. A thorough analysis of the inverter circuit has been carried out through mixed-mode simulation and the effect of the composition of the barrier layer in the GaN-HEMT, as well as the supply voltage of the inverter has been reported. With Si-technology reaching its bottleneck, GaN based device circuits will surely foster further research in this domain.

A Low-Power Microwave HEMT $LC$ Oscillator Operating Down to 1.4 K

High-electron-mobility transistors (HEMTs) based on 2-D electron gases (2DEGs) in III–V heterostructures have superior mobility compared with the transistors of silicon-based complementary metal–oxide–semiconductor technologies. The large mobility makes them attractive not only for low-noise and high-power microwave applications but also for low-power applications down to deep cryogenic temperatures. Here, we report on the design and characterization of a low-power HEMT LC Colpitts oscillator operating at 11 GHz whose minimum power consumption is $90~\mu \text{W}$ at 300 K and $4~\mu \text{W}$ at 1.4 K. The fully integrated oscillator is based on a single HEMT transistor having a gate length of 70 nm and realized using a 2DEG in In0.7Ga0.3As. The power consumption of the realized oscillator is the lowest reported in the literature so far for an LC oscillator operating in the same frequency range. In order to investigate the behavior of the oscillator, we also performed a detailed characterization of a stand-alone HEMT transistor from 1.4 to 300 K with a static magnetic field from 0 to 8 T. From the extracted values of the transistor parameters, we estimate and compare the minimum power necessary to start-up oscillations for two different Colpitts topologies.

Elemental behaviors of InGaAs surface after treatment in aqueous solutions

Indium gallium arsenide (InGaAs) is one of the candidates as a channel material for the high-performance complementary metal-oxide-semiconductor (CMOS) devices superior to silicon-based CMOS devices because of its higher electron mobility. In order to introduce InGaAs as a new channel material for high-performance CMOS devices, it is important to prepare its surface to suppress material loss and surface oxide formation in the InGaAs layer. In this study, the behavior of each element of the In0.53Ga0.47As surface in chemical solutions such as HCl, NH4OH, HPM (HCl/H2O2/H2O) and APM (NH4OH/H2O2/H2O) was investigated from the viewpoint of thermodynamics and reaction kinetics. In the acidic HCl solution, the dissolution of the InGaAs surface was the dominant reaction, whereas a sub-oxide formed on the InGaAs surface in the basic NH4OH solution. The formation of the oxide on the surface was considered the rate-limiting step of the overall etching reaction of InGaAs in the acidic solution; therefore, the surface oxidation and overall etching (dissolution) of the InGaAs layer were determined using different amounts of H2O2 in the solution. In particular, the overall etching of the InGaAs surface in the HPM solution was more aggressive than that in the APM solution. The behavior of InGaAs in the surface preparation process sequences with APM, HPM, and HF was also investigated, and it was observed that the material loss and surface roughening of the InGaAs layer were mostly determined in the HPM process. Finally, it was possible to suppress the surface oxidation, material loss, and surface roughening of the InGaAs layer by reducing the concentration of H2O2 in the HPM solution.

Recent progress in two-dimensional transition metal dichalcogenides: Material synthesis for microelectronics

The size of modern electronic and optoelectronic devices has been shrunk down to nanoscale and this effort still continues. A lot of concerns focus on whether current silicon-based complementary metal oxide semiconductor (CMOS) technologies can overcome the physical limit at nanoscale. A promising alternative choice of semiconductor material, two-dimensional layered materials (2DLMs) have emerged recently, including graphene, 2D transition-metal dichalcogenides (2D TMDs), black phosphors (BPs), etc. Due to their unique atomic thickness nature, 2DLMs are likely to have the greatest potential to overcome the dilemma of geometric scaling. 2DLMs also exhibit a wide range of unique properties owing to their unusual atomically thin defined structures. Most 2D TMDs have a MX2 structure, where M represents transition metal (Mo, W, Ti, Pt, Hf, etc.) and X is the chalcogen (S, Se, or Te). Contrary to graphene which displays many superior properties but lacks a bandgap, 2D TMDs exhibit a wide range of electronic properties, from semiconducting to metallic or even superconducting, depending on the combination of M and X. For most Mo and W based 2D TMDs, the intrinsic band gap is greater than 1 eV so that the high on/off-current ratio is more easily achieved at room temperature. Moreover, 2D TMDs possess band structures that are known to be highly sensitive to various effects that arise from surfaces and interfaces, thus providing versatile knobs for tuning 2D TMD devices. Various modification methods have been applied to further physically or chemically tune 2DLMs based on their unique intrinsic properties. To date these include dimensional sizing, ion-intercalation, application of an external field, tuning the stacking order, and strain engineering, etc. These fundamental modification methods provide useful engineering tools to improve TMD electronic devices. So far, most research results of 2D TMDs have been based on mechanically exfoliated sheets which are single crystalline with few defects. But the exfoliation method has poor reproducibility, relatively low yield, and gives rise to a lateral size no more than hundreds of microns. Thus, the main bottleneck for practical application of 2D TMDs in electronic devices still remains at the stage of wafer scale uniform growth. Compared to chemical vapor deposition (CVD) synthesized graphene film with high carrier mobility and large grain size, the existing synthetic methods of 2D TMDs can only produce films with limited spatial uniformity and fair electrical performance. Thus, there is still significant room for improving current CVD methods, or exploring new synthetic methods. In this review, we summarize and compare various preparation methods of 2D TMD materials. All these methods can be actually classified by two strategies: ″Top-down″ methods, where the bulk forms are exfoliated into few-layer or monolayer sheets; and the ″bottom-up″ methods, that chemically synthesize 2D TMDs using CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc. We first introduce several important ″Top-down″ methods including mechanical exfoliation, liquid phase exfoliation, ion intercalation and laser thinning. We then focus on the CVD approaches that are suitable for wafer-scale synthesis of high-quality 2D TMD films. We also introduce the latest development of 2D TMDs application in electronic devices, and provide a look at the future of this field.

A post-CMOS compatible smart yarn technology based on SOI wafers

Smart yarn and intelligent textiles have been extensively researched recently due to their significant roles in various entertainment, healthcare and military applications. However, most smart yarns and textiles developed so far do not come with sophisticated functionality due to the difficulty of integrating silicon-based sensors and CMOS (complementary metal-oxide-semiconductor) circuits. This paper reports an SOI (silicon-on-insulator)–CMOS compatible technology to fabricate smart yarn, enabling the monolithic and invisible integration of CMOS and sensors. A tubular shaped parylene smart yarn design with a reinforcing polydimethylsiloxane (PDMS) core has been developed. Isotropic XeF2 silicon etching and conformal parylene coating were used to form the outer shell and release the electronic/sensing components from an SOI wafer. To prove the concept, silicon strain gauges and MOSFETs (metal-oxide-semiconductor field-effect-transistors) were integrated. Human arterial blood pulse detection on the wrist by a smart yarn fiber integrated with a silicon strain gauge has been demonstrated.

Modeling of Physical Defects in PN Junction Based Graphene Devices

Graphene's exceptional electro-mechanical properties make it a strong contender to replace silicon-based Complementary Metal-Oxide Semiconductor (CMOS) devices in the future. Among other novel material-based devices, graphene is pushing the research community to find new technological solutions that exploit its special characteristics. As it is a semimetal, the key challenge for graphene-based devices to be used in digital circuits is introducing band gap. Among the proposed approaches, electrostatic doping represents a key option. It allows the implementation of graphene pn junctions through which building a new class of reconfigurable logic gates is possible. This devices are analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22 nm. This paper explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. Two major kinds of manufacturing defects, which are possible in these gates, namely the S h o r t s between the device's terminals and O p e n terminals, are considered. These faults have been injected into non faulty devices at the SPICE-level and the resulting behavior is mapped to appropriate fault model. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.