Signed Digit Format Research Articles

Architectures for multiple constant decimal multiplication

Due to the increasing demand for decimal calculations in the business, financial and economic world, decimal arithmetic circuits have been much considered by system designers. This is mainly because, these applications heavily depend on decimal arithmetic since the results must match exactly those obtained by human calculations. While decimal multiplication is one of the most frequent and complex-to-implement decimal operations, the special case of constant decimal multiplication is widely used in the economic and financial applications. In this paper, we propose two ideas, named “Constant Decimal TCSD” (CDT) and “Constant Decimal DDDS” (CDD), and their hardware implementations for realizing multiple constant decimal multiplication. In the CDT and CDD architectures, the partial products are generated using a set of positive multiplicand multiples coded in2′s complement signed-digit format (TCSD) and binary coded decimal (BCD), respectively. We also present two new (3:1) compressors to reduce the number of partial products in both designs, one based on a new Double Decimal Digit Set (DDDS), which is not only self-complementing but also its redundancy, allows carry-free addition. Finally, a redundant to non-redundant converter recodes the TCSD and DDDS product to BCD in the first and second schemes, respectively. Hardware synthesis evaluation shows that compared to the most recent 16 × 16 decimal multipliers, delay, area, power consumption and PDP of the proposed multiple constant multipliers improve up to 57%, 89%, 93% and 97%, respectively.

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are meant for reducing computational complexity in digital adaptive filters in denoising electrocardiogram signals. In adaptive filtering using Sign-Sign algorithm, the adders and multipliers in the existing method take the coefficients in canonic signed power of two form which assures that between two non-zero there should be one zero in signed power of two digits and they can process only one bit per clock cycle and so is the filter resulting in low speed. In this paper, digit serial adder and digit serial multiplier are proposed to design the Sign-Sign Least Mean Square filter, which increases the speed by processing two bits per clock cycle. The digit serial adder and digit serial multiplier are used to design the Sign-Sign based adaptive filter in which unfolding technique is used for digit serial realisation. The unfolding factor of K = 2 is chosen to increase the speed of the design. The coefficients and its inputs are represented in Canonic Signed Digit form. Adder, multiplier, adaptive filter of both existing and proposed method are simulated using Mentor Graphics and synthesised using Synopsys Design Compiler Tool with 90 nm technology. From the results it is observed that the speed of the proposed digit serial Sign-Sign Least Mean Square filter is increased by 54.5% and the area of the filter is decreased by 4.21% compared to the bit serial Sign-Sign Least Mean Square filter.

High Performance Methods of Elliptic Curve Scalar Multiplication

Elliptic curve scalar multiplication is the operation of successively adding a point along an elliptic curve to itself k times. It is used in elliptic curve cryptography (ECC) as a means of producing a trapdoor function. In this paper, algorithms to compute the elliptic curve scalar multiplication using a special form for integers will introduce, and then two types of signed digit representation will use. The signed digit form of the scalar is calculated by many types of algorithms such as binary , non adjacent form and direct recoding. The results indicate that the proposed methods perform better to compute the scalar multiplication on elliptic curves and it is more efficient than the existing methods.

Decimal Division Algorithms: The Issue of Partial Remainders

The efficiency of decimal digit-recurrence division algorithms is totally affected by the number representations of the quotient, the divisor and partial remainders participated in quotient digit selection (QDS). This paper establishes general rules and conditions for QDS with operands represented in the generalized signed-digit format. As a result of this generalization, a universal convergence condition is introduced which obviates the unnecessary conservatism of previous algorithms and hence paves the way for more correct and efficient decimal division hardware designs. It is also concluded that keeping the partial remainders in minimally redundant symmetric signed-digit representation (with digit-set [?5,6])and applying into QDS the divisor represented in minimally asymmetric non-redundant signed-digit format (with digit-set [?4,5]) lead to the smallest minimum precision required, of the divisor and the partial remainder, for QDS and thus faster and simpler division algorithm. Moreover, it is shown that even in case of using non-redundant partial remainders (for the sake of lower area cost); minimally asymmetric signed-digit representation brings about more efficiency. The suggested representations are applied to the fastest previous decimal digit-recurrence divider and 10 % speed-up is achieved while keeping the area cost approximately unaltered.

A novel implementation of radix-4 floating-point division/square-root using comparison multiples

A new implementation for minimally redundant radix-4 floating-point SRT div/sqrt (division/square-root) with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the magnitude of the quotient (root) digit is calculated by comparing the truncated partial remainder with 2 limited precision multiples of the divisor (partial root). The digit sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using the logical synthesis (Synopsys DC with Artisan 0.18 μm typical library) shows a latency of 2.5 ns for the recurrence of the proposed div/sqrt. This is less than of the conventional implementation.

A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples

A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the quotient digit's magnitude is calculated by comparing the truncated partial remainder with two limited precision multiples of the divisor. The sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using logical synthesis shows a latency of 2.34 ns for the recurrence of the proposed divider. It is ∼22% less than the conventional implementation.

Fast decimal floating-point division

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division with the recurrence in a new decimal signed-digit format. Quotient di...

Fast Decimal Floating-Point Division

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

Radix 2 division with over-redundant quotient selection

In this paper we present a new radix 2 division algorithm that uses a recurrence employing simple 3-to-2 digit carry-free adders to perform carry-free addition/subtraction for computing the partial remainders in radix 2 signed-digit form. The quotient digit, during any iteration of the division recursion, is generated from the two most-significant radix 2 digits of the partial remainder and independent of the divisor in over-redundant radix 2 digit form (i.e., with digits which belong to the digit set {-2, -1, 0, +1, +2}). The over-redundant quotient digits are then converted to the conventional radix 2 digits (belonging to the set {-1, 0, +1}) by using a reduction technique. This division algorithm is well suited for IEEE 754 standard operands belonging to the range (1, 2) and is slightly faster than previously proposed radix 2 designs (such as the radix 2 SRT), which do not employ input scaling, since the quotient selection for such algorithms is a function of more than two most-significant radix 2 digits of the partial remainder. In comparison with the designs that employ input scaling, the proposed design although slightly slower saves hardware required for scaling purposes.

Decimal Adder with Signed Digit Arithmetic

Addition algorithm, decimal adder with signed digit arithmetic p presented here was designed to establish the following facts: the redundant representation of a decimal digit xi by a 5-bit binary number Xi=3xi leads to a logical design of extreme simplicty; it is possible to form an additional algorithm for the adder so that it can be used to transform numbers written in a conventional decinal form into a signed digit form, and vice versa.