Signal To Quantization Noise Ratio Research Articles

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order

This brief presents a two-phase multi-bit incremental analog-to-digital converter (IADC) with variable loop order. In the 1st phase, the loop filter works as a 1st-order topology. In the 2nd phase, the loop reconfigures to a 3rd-order structure, aiming to get the signal-to-quantization-noise ratio (SQNR) boosted quickly within a few clock cycles. Such a two-phase scheme with variable loop-order combines the features of the KT/C noise suppression and high effectiveness of data weighting averaging (DWA) presented by the 1st-order IADC and fast accumulation obtained from the high-order mode. Thereby, with little additional circuitry effort, the proposed IADC improves DWA effectiveness while mitigating the thermal noise penalty when compared with a pure high-order IADC. The proposed architecture is analytically analyzed and exemplarily simulated. Moreover, a design guideline is provided to optimize the allocation of the clock cycles of two phases, thus balancing various significant parameters. Based on the guideline, a circuit-level simulation of an exemplary 1st-to-3rd order IADC was carried out in a 65-nm CMOS process to confirm the results.

Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

Pre-Equalized DMT Signal Transmission Utilizing Low-Resolution DAC With Channel Response Dependent Noise Shaping Technique

In this paper, a channel response dependent noise shaping (CRD-NS) technique is proposed and experimentally demonstrated for the pre-equalized discrete multi-tone (DMT) signal transmission in intensity modulation and direct detection (IM/DD) system with a low-resolution digital-to-analog converter (DAC). Compared with traditional NS technique, the proposed CRD-NS technique can bring signal-to-quantization noise ratio (SQNR) improvement and solve the unevenly distributed SQNR problem in pre-equalized DMT signal induced by residual quantization noise without introducing additional computational complexity. Transmission and reception of 100 Gb/s 16 quadrature amplitude modulation (QAM)-DMT signal generated by a 3-bit DAC are experimentally demonstrated to verify the effectiveness of the proposed CRD-NS technique. The experimental results show that the bit-error ratio (BER) performance of 100 Gb/s 16 QAM-DMT signal with CRD-NS technique outperforms the corresponding signal with traditional NS technique. Compared with digital resolution enhancer (DRE) technique, in which channel response is also considered, the CRD-NS technique shows a similar noise shaping capability with DRE in pre-equalized DMT signal transmission, while the computational complexity can be significantly reduced, the number of real multiplications per sample is reduced from 81 to 7.

Analysis and Design Optimization of a 2-Path Sigma Delta Modulator

This paper presents a new design for the optimization of analog to digital sigma delta-coupling noise annotations. The proposed technique increases the level of the signal-to quantization-noise-ratio (SQNR) by improving the zero of the noise transfer function, which leads to an increase in signal to noise. In the new SQNR design, the modulator rises up to 8.5 db. The proposed structure of the first-order dual-channel sigma-delta modulator is also presented.

Performance of Post-Training Two-Bits Uniform and Layer-Wise Uniform Quantization for MNIST Dataset from the Perspective of Support Region Choice

This paper contributes to the goal of finding an efficient compression solution for post-training quantization from the perspective of support region choice under the framework of low-bit uniform quantization. The decision to give preference to uniform quantization comes from the fact that support region choice is the most sensitive in the uniform quantization of nonuniform sources (e.g., Laplacian sources). Therefore, in this paper, we analyse in detail how the choice of the support region influences the performance of two-bits uniform quantization, measured with signal to quantization noise ratio (SQNR), and the accuracy of the compressed neural network (NN) model. We provide experimental and theoretical results for a few significant cases of two-bits uniform quantizer design, where we assume that Laplacian source models the distribution of weights in our fully connected NN. We opt for Laplacian distribution since it models well weights of NNs. Specifically, we analyse whether it is possible to apply the simplest uniform quantization in trained NN model weight representation with a bit rate of R = 2 bit/sample while preserving the accuracy of the model to a great extent. Also, our goal is to determine whether the choice of the key parameter of two-bits uniform quantizer (support region threshold) equally reflects on both, SQNR and accuracy. Moreover, we extend our analysis to the application of layer-wise two-bits uniform quantization in order to examine whether it is possible to achieve an additional improvement of the accuracy of our NN model for the MNIST dataset. We believe that the detailed analysis of post-training quantization described and conducted in this paper is very useful for all further research studies of this very current topic, especially due to the fact that the problem regarding post-training quantization is addressed from a particularly important perspective of choosing the support region.

A 178.9-dB FoM 128-dB SFDR VCO-Based AFE for ExG Readouts With a Calibration-Free Differential Pulse Code Modulation Technique

This article presents a voltage-controlled oscillator (VCO)-based analog front end (AFE) for ExG readout applications with both a wide dynamic range (DR) and high linearity. By using a differential pulse code modulation (DPCM) technique, VCO non-linearity is mitigated by operating the VCO in the small-signal linear regime. To minimize power consumption from the power-hungry gain error calibration, the effect of VCO gain variation within the DPCM loop is investigated, leading to a calibration-free DPCM via a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> truncator. At the circuit level, a coarse–fine phase decoding scheme is proposed to increase signal-to-quantization-noise ratio (SQNR) while avoiding metastability issues. Fabricated in 65 nm, the AFE occupies an area of 0.056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves 94.2-dB SNDR and 95.1-dB DR in 500 Hz of bandwidth while dissipating 1.68- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power from a single 0.8-V supply, yielding a Schreier FoM of 178.9 dB. Importantly, the techniques enable a virtually distortion-less spectrum with a noise-floor limited spurious-free dynamic range (SFDR) of 128 dB. In addition, the AFE is validated with ECG and EOG recording, demonstrating complete signal capturing in the presence of motion/stimulation artifacts.

Quantization of Weights of Neural Networks with Negligible Decreasing of Prediction Accuracy

Quantization and compression of neural network parameters using the uniform scalar quantization is carried out in this paper. The attractiveness of the uniform scalar quantizer is reflected in a low complexity and relatively good performance, making it the most popular quantization model. We present a design approach for the memoryless Laplacian source with zero-mean and unit variance, which is based on iterative rule and uses the minimal mean-squared error distortion as a performance criterion. In addition, we derive closed-form expressions for SQNR (Signal to Quantization Noise Ratio) in a wide dynamic range of variance of input data. To show effectiveness on real data, the proposed quantizer is used to compress the weights of neural networks using bit rates from 9 to 16 bps (bits/sample) instead of standardly used 32 bps full precision bit rate. The impact of weights compression on the NN (neural network) performance is analyzed, indicating good matching with the theoretical results and showing negligible decreasing of the prediction accuracy of the NN even in the case of high variance-mismatch between the variance of NN weights and the variance used for the design of quantizer, if the value of the bit-rate is properly chosen according to the rule proposed in the paper.

General Bitwidth Assignment for Efficient Deep Convolutional Neural Network Quantization.

Model quantization is essential to deploy deep convolutional neural networks (DCNNs) on resource-constrained devices. In this article, we propose a general bitwidth assignment algorithm based on theoretical analysis for efficient layerwise weight and activation quantization of DCNNs. The proposed algorithm develops a prediction model to explicitly estimate the loss of classification accuracy led by weight quantization with a geometrical approach. Consequently, dynamic programming is adopted to achieve optimal bitwidth assignment on weights based on the estimated error. Furthermore, we optimize bitwidth assignment for activations by considering the signal-to-quantization-noise ratio (SQNR) between weight and activation quantization. The proposed algorithm is general to reveal the tradeoff between classification accuracy and model size for various network architectures. Extensive experiments demonstrate the efficacy of the proposed bitwidth assignment algorithm and the error rate prediction model. Furthermore, the proposed algorithm is shown to be well extended to object detection.

Near-Field Coherent Sensing of Vibration With Harmonic Analysis and Balance Signal Injection

The near-field coherent sensing (NCS) system can detect weak cyclic motion inside living bodies, such as human wrist pulses and the heartbeat of small animals. To couple significant energy to the motion source, a GHz RF carrier was employed, where the vibration amplitude was often much smaller than the wavelength. To optimize the signal quality, we presented a small-signal model with nonlinearity analysis by Jacobi–Anger expansion. The quiescent-point determination and signal composition were then discussed to guide the hardware and algorithm design. The model was validated by electromagnetic simulation in CST Studio and a simple robotic platform. A novel algorithm of adaptive control by signal injection was applied to boost both the signal magnitude and data converter utilization. The signal-to-quantization-noise ratio (SQNR) is improved by 35 dB and signal-to-noise ratio (SNR) by more than 10 dB. Sensing of vocal cord vibration was demonstrated as a potential application, where a harmonic radio frequency identification (RFID) system was chosen for its low noise floor to achieve high-fidelity recording of music scales and procedure words.

Symmetric Quantile Quantizer Parameterization for the Laplacian Source: Qualification for Contemporary Quantization Solutions

In this paper, we consider the opportunities and constraints, which rest on quantization as a guiding principle for data representation and compression. In particular, we propose a novel model of Symmetric Quantile Quantizer (SQQ) and we describe in detail its parameterization. We suggest a simple method for offline precalculation of its parameters and we examine the inevitable loss of information introduced by SQQ, as an important part of bit optimization task at the traditional network level, which can be globally mapped out in many contemporary solutions. Our anticipation is that such precalculated values can be leveraged in deterministic quantization process. We highlight that this notice heavily relies on the fact that the values of interest are distributed according to the Laplacian distribution, which we consider in the paper. The basic difference of our SQQ and the previously established asymptotically optimal quantizer model, that is, Scalar Companding Quantizer (SCQ), is reflected in the fact that, in SCQ model, both decision thresholds and representation levels are determined in accordance with the specified compressor function, whereas in our SQQ model, a precedence of SCQ model for the straightforward decision thresholds calculation is used, while the representation levels are optimally determined for the specified decision thresholds and assumed Laplacian distribution. As a result, our SQQ outperforms SCQ in terms of signal-to-quantization noise ratio (SQNR). As stated in this paper, there are numerous indications to make us believe that appropriate quantizer parameterization will move us closer to an optimization in the amount of the transferred data in bits, which is strongly dependent on the amount of SQNR.

Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter

This brief proposes an analog-to-digital converter (ADC) based on Generalized Sampling Theorem and derives a closed form expression of its performance, viz., signal-to-quantization noise ratio (SQNR) and alias-suppression (AS). The ADCs in the 2-channels sample the signal and its filtered version, respectively, at half the Nyquist rate. The outputs of the two ADCs are upsampled by a factor of 2, passed through appropriate reconstruction filters, and then added to give an effective sample-rate which is double that of the sample-rate of each channel ADC. Performance of the proposed ADC has been summarized for simple filters like differentiator, integrator, passive RC low-pass filter, and passive CR high-pass filters. The proposed ADC could therefore be used as an alternative to other popular ADC structures like time-interleaved, frequency-interleaved, and filter-bank ADCs, to achieve high sample-rate with minimal analog circuit overhead.

MXQN:Mixed quantization for reducing bit-width of weights and activations in deep convolutional neural networks

Quantization, which involves bit-width reduction, is considered as one of the most effective approaches to rapidly and energy-efficiently deploy deep convolutional neural networks (DCNNs) on resource-constrained embedded hardware. However, bit-width reduction on the weights and activations of DCNNs seriously degrades accuracy. To solve this problem, in this paper we propose a mixed hardware-friendly quantization (MXQN) method that applies fixed-point quantization and logarithmic quantization for DCNNs without the necessity to retrain and fine-tune the DCNN. Our MXQN algorithm is a multi-staged process where, first, we employ a signal-to-quantization-noise ratio (SQNR) process as the metric to estimate the interplay between the parameter quantization errors of each layer and the overall model prediction accuracy. Then, we utilize a fixed-point quantization process to quantize weights, and depending on the SQNR metric we empirically select either a logarithmic or a fixed-point quantization process to quantize activations. For improved accuracy, we propose an optimized logarithmic quantization scheme that affords a fine-grained step size. We evaluate the performance of MXQN utilizing the VGG16 network on the MNIST, CIFAR-10, CIFAR-100, and the ImageNet datasets, as well as VGG19 and ResNet (ResNet18, ResNet34, ResNet50) networks on the ImageNet, and demonstrate that the MXQN-quantized DCNN despite not being retrained and fine-tuned, it still achieves high accuracy close to the original DCNN.

The JM-Filter to Detect Specific Frequency in Monitored Signal

The Discrete Fourier Transform (DFT) is a mathematical procedure that stands at the center of the processing inside a digital signal processor. It has been widely known and argued in relevant literature that the Fast Fourier Transform (FFT) is useless in detecting specific frequencies in a monitored signal of length N because most of the computed results are ignored. In this paper, we present an efficient FFT-based method to detect specific frequencies in a monitored signal, which will then be compared to the most frequently used method which is the recursive Goertzel algorithm that detects and analyses one selectable frequency component from a discrete signal. The proposed JM-Filter algorithm presents a reduction of iterations compared to the first and second order Goertzel algorithm by a factor of r , where r represents the radix of the JM-Filter. The obtained results are significant in terms of computational reduction and accuracy in fixed-point implementation. Gains of 15 dB and 19 dB in signal to quantization noise ratio (SQNR) were respectively observed for the proposed first and second order radix-8 JM-Filter in comparison to Goertzel algorithm.

Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures

This paper presents signal processing methods to enhance the energy vs. accuracy trade-off of in-memory computing (IMC) architectures. First, an optimal clipping criterion (OCC) for signal quantization is proposed in order to minimize the precision of column analog-to-digital converters (ADCs) at iso-accuracy. For a Gaussian distributed signal, the OCC is shown to reduce the column ADC precision requirements by 3 bits at an signal-to-quantization noise ratio (SQNR) of 22.5 dB over the commonly used full range (FR) quantizer. Next, the input-sliced weight-parallel (ISWP) IMC architecture is presented as a generalization of the popular bit-serial bit-parallel (BSBP) architecture. Quantization noise analysis of the ISWP indicates that its accuracy is comparable to BSBP while providing an order-of-magnitude reduction in energy consumption due to fewer array invocations and smaller ADC precision. Combining OCC and ISWP noise analysis, we map popular DNNs such as VGG-9 (CIFAR-10), ResNet-18 (CIFAR-10), and AlexNet (ImageNet) on a OCC-enabled ISWP architecture and show a reduction in energy consumption by an order-of-magnitude at iso-accuracy over the BSBP architecture that employs FR-based ADCs.

Fusion of dynamic predictive block adaptive quantization and vector quantization for staggered SAR data compression

ABSTRACT Staggered synthetic aperture radar (SAR) is an advanced concept for high-resolution wide-swath (HRWS) imaging, which overcomes the problem of blind ranges by continuously varying the pulse repetition frequency (PRF). For better performance of information recovery in blind ranges, data are typically highly oversampled in azimuth for staggered SAR system. Thus a huge data volume onboard is required and the demands for internal data storage and downlink capacity are increasing. In this paper, we investigate a novel method, named Dynamic Predictive Block Adaptive Vector Quantization (DP-BAVQ), to reduce the volume of downlinked data for staggered SAR. It firstly compresses the difference of the raw data and their predictions with the dynamic predictive block adaptive quantization (DP-BAQ). Then a secondary compression is performed with vector quantization (VQ). The simulation results and the experiments with real data show that the proposed method achieves an improvement in the signal-to-quantization noise ratio (SQNR) compared with DP-BAQ. Moreover, DP-BAVQ at 2 bits/sample provides a higher SQNR compared with standard block adaptive quantization (BAQ) at 3 bits/sample. Thus the proposed method allows for a significant reduction of data volume.

An improved MASH sigma-delta modulator with all-anolog interstage and input-feedforward architecture

ABSTRACT This paper puts forward an improved multi-stage noise-shaping (MASH) sigma-delta modulator. Derived from a fourth-order two-stage MASH architecture with adder-less architecture of cascade of integrators with feedforward (CIFF), the proposed modulator improves the method of extracting quantization noise of the first stage to form an all-analog interstage, and two input-feedforward paths are added to the second stage to reduce the output swing of the integrator. Analyses and measurements indicate that the proposed architecture has lower in-band quantization noise power, higher signal-to-quantization noise ratio (SQNR), and lower power consumption and complexity as well. When operating from a 1.2 V supply, the modulator achieves 107.56 dB peak SQNR, 71.8 dB peak Signalnoise and distortion ratio while consuming 26 mW, with an OSR of 8 at a 160 MHz sampling frequency.

Tunable Block Floating-Point Quantizer With Fractional Exponent for Compressing Non-Uniformly Distributed Signals

Block floating point quantization (BFPQ) exploits signal statistics so that one common exponent is shared among a block of data. The output signal-to-quantization-noise ratio (SQNR) may drop due to the increase in quantization error resulted from the increment of the exponent, especially for the non-uniformly distributed input signals. The tunable BFPQ is then proposed. With the aid of the tuning parameter to enlarge the thresholds for deciding the exponent and fractional exponent, the quantization error and saturation error can be balanced and thus the output SQNR can be sustained as high as possible. Both the analytic and simulated results are provided to verify the effectiveness of the tuning parameter for Gaussian-distributed and Laplacian-distributed signals. The improvement in output SQNR compared to the conventional BFPQ is also shown. Finally, the concept is implemented to support real-time high-speed compression for high-resolution synthetic aperture radar image applications. We demonstrate that the tunable BFPQ can be accomplished with only a small overhead but brings substantial performance gain, especially for large data blocks.

A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators

This paper presents a dynamic power reduction technique for incremental $\Delta \Sigma $ (I- $\Delta \Sigma $ ) modulators. The technique makes use of the unequal weighting of the digital reconstruction filter. The underlying idea is that the input signal samples are not equally weighted in the higher order reconstruction filter. Thus, it is possible to increase the non-idealities of the I- $\Delta \Sigma $ modulator during the runtime of a single Nyquist conversion, thereby saving power. This principal idea is verified by an example design, where the input-referred noise of the first integrator is dynamically increased, which allows for improved efficiency. The proposed technique is readily applicable to every state-of-the-art I- $\Delta \Sigma $ modulator. Furthermore, it is shown that this property can also be used to switch a single-bit digital-to-analog converter (DAC) into a multibit DAC during runtime, thereby greatly improving the achievable signal-to-quantization-noise ratio (SQNR) without suffering from the DAC non-linearity. The prototype I- $\Delta \Sigma $ modulator is manufactured in a 180-nm CMOS technology and achieves a dynamic range/SNDR = 91.5/86.6 dB for a sampling rate of 200 kS/s while consuming l.l mW from a 3-V supply, while the dynamic power reduction method accounts for 30% power savings.

A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS

This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.

On the Design of Optimal Noise Transfer Functions for Delta–Sigma Modulators

One of the popular methods of designing a noise transfer function (NTF) used in the synthesis of a delta–sigma modulator (DSM) is to optimally place its zeros across the signal band of interest while minimizing the in-band noise power. The distribution of the poles of the NTF is considered secondary. In this brief, we provide a method to design a discrete-time NTF from a normalized analog highpass filter in which the coefficients of the characteristic polynomial of the squared-magnitude function of the filter are optimized to minimize the energy in the band of interest, in addition to satisfying the realizability constraints required to synthesize a DSM. We compare the performance of the NTFs designed using our method with those designed using one of the well-known methods in terms of the signal-to-quantization noise ratio (SQNR). It is shown that the SQNR of the NTFs designed using our method is higher than that of the NTFs designed using the well-known methods.