Signal-to-noise Plus Distortion Research Articles

A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators

This paper presents an innovative general structure for a single-loop Sigma-Delta ([Formula: see text]) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6[Formula: see text]dBFS and a sampling frequency of 2.56[Formula: see text]MHz, the signal to noise plus distortion (SNDR) was 81.9[Formula: see text]dB, and the dynamic range (DR) was 88[Formula: see text]dB for a 20[Formula: see text]KHz bandwidth. The modulator’s power consumption was 126.9[Formula: see text][Formula: see text]W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

Inverter-based noise-shaping SAR ADC for low-power applications

Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs among power dissipation, adequacy for scaling with technology, performance, and robustness against process-voltage-temperature (PVT) variations. In this work, a NS SAR ADC realization, based on inverter-based amplification, is proposed that alleviates these design challenges. The proposed implementation is used to design two ADCs in 28 nm CMOS technology to demonstrate its effectiveness. The first ADC employs an active loop-filter and achieves a signal-to-noise-plus-distortion (SNDR) of 62.9 dB, at a sampling frequency of 90 MHz, and an oversampling ratio (OSR) of 4, while consuming 0.59 mW from a 0.9 V supply. The second ADC has a passive loop-filter and provides 61 dB of SNDR for the same OSR and sampling frequency, with 0.58 mW power dissipation.

A Reference Voltage Circuit Applied in High Precision Delta-Sigma ADC

A novel reference voltage circuit design which is applied in high-precision Delta-Sigma ADC is implemented. The proposed reference circuit exploits a high-gain class-AB OTA as the error amplifier, which improves the transient response characteristics, ensures loop stability, and does not increase additional power consumption. The design and simulation of the proposed reference voltage circuit are fabricated by SMIC.18 CMOS technology. The simulation results manifest that the temperature coefficient of the bandgap reference is 6.825 ppm/°C in the temperature range from -40°C to 125°C. The transient response of the proposed reference circuit takes about 13 ns to reach the precision demanded by the reference voltage. The Σ-Δ modulator with the designed reference voltage circuit applied has an effective number of bits (ENOB) of 18.1 bits, a signal-to-noise-ratio (SNR) of 111.2 dB, and a signal-to-noise-plus-distortion (SNDR) of 110.9 dB at 1MHz sampling frequency and 625 Hz input signal.

PN-assisted digital background calibration of two-step ADC to over 14-bit accuracy

A new non-binary multiplying digital-to-analog converter (MDAC) structure with signal-dependent dithering scaling technique is proposed in this paper. A full digital background calibration algorithm based on pseudo-random dithers injection is used to calibrate the nonlinear errors of MDAC. By measuring sampling capacitor mismatch and op-amp gain errors of the pipelined analog-to-digital converter (ADC) in background, the errors will be greatly reduced by the proposed calibration algorithm. At the same time, the signal-dependent dithering scaling technique provides a swing margin to the injected pseudo-random signal. By using this technique, the errors caused by the capacitor mismatch and op-amp gain errors can be calibrated at the same time. What’s more, this method greatly accelerates the convergence speed. A two-stage 14-bit pipelined ADC is used to simulate and verify the proposed algorithm. The simulation results indicate the effectiveness of the technique, in which the signal-to-noise plus distortion (SNDR) and the spurious-free dynamic range (SFDR) performance of a 14-bit two-step ADC are improved from 49.12 and 56.25 to 85.68 and 102.23 dB with the input frequency being 0.06 * f s , respectively. The SFDR is more than 98 dB. The SNDR reaches 84 dB in the whole Nyquist bandwidth after calibration. Integral nonlinearity is improved from 80 to 1.5 least significant bits after calibration.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter (RSD-ADC) is presented featuring a high signal to noise ratio (SNR), spurious free dynamic range (SFDR) and signal to noise plus distortion (SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC (residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

MOSFET-ONLY TWO-STAGE OPERATIONAL AMPLIFIERS WITH MILLER COMPENSATION: DESIGN AND FABRICATION IN NANO-SCALE CMOS

Nano-scale area-efficient MOS devices are employed in this article to stabilize high-speed operational amplifiers (opamps) for those applications that deal with negative feedback. As an alternative choice, metal-insulator-metal (MIM) capacitors cannot be integrated in every technology as they require additional process masks. Moreover, these components suffer from large silicon area. In this paper, considerations of a successful MOSFET-only amplifier design are highlighted and described. These considerations make it possible to fabricate these amplifiers for a nano-scale digital system-on-chip (SoC). Circuit-level simulations include comparison between MOS capacitors (MOSCAPs) with MIM capacitors (MIMCAPs) in two identical processes. The efficiency of the given design considerations are also validated through simulation in 90-nm CMOS technology. A MOSFET-only amplifier is designed as the main part of a 5 MS/s sample-and-hold. Using the proposed design techniques, the MOSFET-only amplifier with Miller compensation recovers 51% silicon die with respect to a MIMCAP amplifier for identical signal-to-noise-plus-distortion (SNDR) ratio.

A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator

A fully differential double-sampled switched-capacitor (SC) architecture for a fourth-order bandpass /spl Sigma//spl Delta/ modulator is presented. This architecture is based on a double-sampled SC delay circuit. The effect of opamp nonidealities (finite dc gain and nonzero input capacitance) on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5-/spl mu/m CMOS technology and operates at a clock frequency of 80 MHz, making the effective sampling rate 160 MHz. The image signal is about 40 dB below the fundamental signal. The measured signal-to-noise-plus-distortion (SNDR) is 47 dB (not including the image) over a 1.25-MHz bandwidth centered at 40 MHz. The circuit operates at 3 V and consumes 65 mW.