Signal Flow Graph Model Research Articles

Parasitic Oscillation Analysis of Trench IGBT During Short-Circuit Type II Using TCAD-Based Signal Flow Graph Model

The oscillation phenomenon of trench-type insulated gate bipolar transistors during short-circuit (SC) type II was investigated experimentally and theoretically. The gate resistance required to suppress oscillations decreased with an increasing collector voltage. The oscillation conditions were calculated from the signal flow graph model using the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S}$ </tex-math></inline-formula> -parameter based on a technology computer-aided design simulation. The calculation results reproduced the locus of the collector voltage dependence of the experimentally measured gate resistance. The oscillation mechanism was investigated using the device simulation. The response of carrier density modulation at the base-drift layer boundary was found to transmit to the collector side through the electron–hole plasma region during the oscillation, indicating that the transfer characteristics of the carrier density modulation in the drift region at the specific collector voltage influence the collector voltage dependence of the SC oscillation. The influence of circuit parameters on the oscillation was also investigated. An increase in the emitter inductance suppressed the oscillations, whereas an increase in gate inductance increases oscillations.

Study of parasitic oscillation of a multi-chip SiC MOSFET circuit based on a signal flow graph model by TCAD simulation

This study presents a novel method to evaluate oscillation condition by technology computer-aided design (TCAD) simulation and is based on a signal flow graph model and a scattering parameter (S-parameter) computed using the TCAD simulation result. The parasitic oscillation of Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) when a short circuit occurs has been investigated with the proposed method. The oscillation conditions of a circuit were computed with this technique and compared with those computed by TCAD transient simulation. The gate resistance to suppress oscillation is similar between these methods. Moreover, the method was also applied to estimate the stability of a circuit consisting of parallelly connected SiC MOSFETs. Two oscillation modes were taken into account. We demonstrated that the circuit parameters required to suppress parasitic oscillation can be computed using a simple calculation.

Signal flow graph model and control of dual input boost converter with voltage multiplier cell

The dual input boost converter (DIBC) with dual boost and integrated voltage multiplier cell (VMC) operating in continuous conduction mode (CCM) at duty cycles larger than 0.5 is a necessity to deliver a high voltage gain for energy systems possessing two independent renewable energy resources (RES). However, the modelling of this higher order converter is challenging due to the overlapping switching signals, multi-stage operation and the parasitic elements. Thus this paper aims to develop the small-signal transfer function model by applying the signal flow graph (SFG) approach. In addition, to handle the output voltage regulation of this converter with unknown load values this paper presents the design of adaptive current-mode (ACM) control using an adaptive law to estimate the uncertain load resistance in terms of load conductance to compute the reference inductor currents. Two independent input inductor reference currents are considered to ensure the decoupling among the interacting loops. The dynamic performance of the ACM controller to handle unknown load and an improved version of a traditional control, the feedforward plus feedback controller for known values of load resistance are designed and assessed. A 200W converter model is built, and the controls are implemented using FPGA.

Ripple base signal flow graph modelling of DC–DC switching converters

A new ripple base signal flow graph (R-SFG) modelling method was proposed to accurately model and analyse a family of switching DC–DC converter. The performance of some DC–DC converters such as single-inductor multi-output converters is dependent on inductor current ripples. This makes the conventional modelling methods cannot fully predict the overall behaviour of converter. From this family and in this study, a single-inductor dual-output (SIDO) boost/boost converter has been modelled based on proposed R-SFG method. The simplicity and systematic procedure presented in this work showed that the R-SFG could be a good alternative for modelling switching converter with complicated structures and with high inductor current ripple. In the new R-SFG method, the effects of inductor current ripple have been considered to develop the conventional signal flow graph modelling method. In this work, a comparative study between two modelling methods has been carried out in a SIDO converter. A step-by-step direct mathematical manipulation was used to calculate the DC–DC transfer function of SIDO converter. The experimental results were included to show the validity of the obtained models. The experimental results showed that the maximum R-SFG modelling error was about 5% over the wide range of inductor current ripple.

Performance and Stability Analysis of Series-Cascaded, High-Gain, Interleaved Boost Converter for Photovoltaic Applications

Abstract Interleaved boost converters (IBCs) are cascaded in parallel in most of the applications. This novel approach connects IBC in series cascade. The IBC has an optimal operating duty cycle of 0.5. Normally, photovoltaic source voltage is low because of space constraints. In order to boost the source voltage, a conventional boost converter is replaced with series-cascaded IBC in this paper. The single-stage IBC also boosts the voltage to twice the input voltage. In the proposed converter, output voltage is about four times the input voltage with the same 0.5 duty cycle. A mathematical model is developed and simulated for the proposed work in MATLAB/Simulink platform. The output of the proposed circuit is analysed through fast Fourier transform to know the harmonic content due to the switching. The system is tested for stability with signal-flow graph modelling. The proposed work is realised using hardware and tested to validate the model.

Signal flow graph modelling of a switching converter with single inductor triple output DC–DC structure

This study describes the systematic signal flow graph (SFG) modelling of a single inductor triple output (SITO) DC/DC converters. The multi-stages operation of SITO converter and the parasitic elements cause obtaining a model to predict the all behaviours of converter be more difficult than typical converters. By SFG method, all small-signal transfer functions can be derived. Derivations of large-signal, small-signal and steady-state models are demonstrated by considering a single inductor triple output boost/boost convert. The effect of inductor ripple current has been considered to determine the acceptable region of SFG modelling method. Simulation and experimental results are included to show the validity of the obtained model.

Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA

Field Programmable Gate Array (FPGA) boast abundant resources with which to realise high-performance accelerators for computationally demanding operations. Highly efficient accelerators may be automatically derived from Signal Flow Graph (SFG) models by using architectural synthesis techniques, but in practical design scenarios, these currently operate under two important limitations - they cannot efficiently harness the programmable datapath components which make up an increasing proportion of the computational capacity of modern FPGA and they are unable to automatically derive accelerators to meet a prescribed throughput or latency requirement. This paper addresses these limitations. SFG synthesis is enabled which derives software-programmable multicore single-instruction, multiple-data (SIMD) accelerators which, via combined offline characterisation of multicore performance and compile-time program analysis, meet prescribed throughput requirements. The effectiveness of these techniques is demonstrated on tree-search and linear algebraic accelerators for 802.11n WiFi transceivers, an application for which satisfying real-time performance requirements has, to this point, proven challenging for even manually-derived architectures.

Analyzing a four quadrant dc-dc Luo converter by means of signal flow graph modeling technique

Abstract In this paper, the signal flow graph technique and Mason gain formula are applied for extracting small signal model and transfer functions from control to output and from input to output. In order to investigate a rather complex system, a four quadrant dc-dc Luo converter known as a second generation and high order power electronic converter is chosen for modeling and analyzing purposes. This converter has received the least attention and its dynamic modeling and analysis is not reported in literature. To get rid of complex equations in modeling high order converters, signal flow graph method is applied to manipulate the equations. Hence, the small signal models for two converters in different states are derived in detail and the obtained models are used to achieve the frequency responses and do stability analysis. The whole paper shows that using the proposed method, derivation of small signal models for all states and frequency domain analysis can be easily carried out in detail.

A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits

This paper proposes a static linear behavior (SLB) analog fault model for switched-capacitor (SC) circuits. The SC circuits under test (CUT) are divided into functional macros including the operational amplifiers, the capacitors, and the switches. Each macro has specified design parameters from the design's perspectives. These design parameters constitute a parameter set which determines the practical transfer function of the CUT. The SLB fault model defines that a CUT is faulty if its parameter set results in transfer functions whose frequency responses are out of the design specification. We analyzed the fault effects of the macros and derived their faulty signal-flow graph models with which the faulty transfer function templates of the CUT can be automatically generated. Based on the templates, we proposed a test procedure that can estimate all the parameters in the parameter set so as to test the CUT with multiple faults. Different from conventional single fault assumption, the proposed SLB fault model covers concurrent multiple parametric faults and catastrophic faults. In addition, it does not need to conduct fault simulations before test as conventional analog fault models do. As a result, it addresses the impractically long fault simulation time issue. A fully-differential low-pass SC biquad filter was adopted as an example to demonstrate how to design and use efficient multitone tests to test for the parameter set. The multitone test results acquired during the test procedure also reveal the distortion and noise performance of the CUT though the SLB fault model does not include them.

A Systematic USFG Design Approach for Integrated Reconfigurable Switched-Capacitor Power Converters

A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load.

Analysis of Fourth-Order DC–DC Converters: A Flow Graph Approach

The signal flow graph (SFG) nonlinear modeling approach is well known for modeling DC-DC converters and it is a powerful analysis tool for higher order converter systems. Modeling of several specific fourth-order DC-DC converter circuits have been reported using conventional state-space averaging. Particular emphasis has been given, so far, only to arrive at any of the large, small-signal (SS) and steady-state models but not a generalized one. This paper gives the generalized SFG model of the fourth-order DC-DC converter topology that is useful for generating different types of fourth-order DC-DC converter circuits unified models. Further, it is shown that the deduction of large, SS and steady-state models from these unified SFGs is easy and straightforward. All possible fourth-order DC-DC converter circuits from its generalized topology have been identified and an analysis of a few converter circuits is given here for illustration of the proposed modeling method. Large-signal (LS) models are developed for different topology configurations and are programmed in SIMULINK simulator. LS responses against supply and load disturbances are obtained. Experimental observations are provided to validate the proposed modeling method.

Graphical Analytical Method for Power DC–DC Converters: Averaging Binary Tree Structure Representation

This letter illustrates a general analytical method for power dc-dc converters called averaging binary tree structure representation. The proposed method, based on switching signal flow graph (SSFG) models, describes the converters as a binary tree structure. General construction principles of the binary tree for the complex flow graph system are summarized and developed. The proposed method has been applied to the analysis for second-order dc-dc converters. It shows the advantages of high convenience and practicability compared with conventional SSFG analytical methods. Simulation and experimental observations are provided to validate the proposed algorithm

Modelling and analysis of cascade step-down converters

Signal flow graph nonlinear modelling of N-cell cascade step-down buck converters is presented. General rules useful for drawing the signal flow graphs are evolved. A systematic procedure for developing a unified flow graph model of the cascade buck converters operating in synchronous control is discussed. A simplified procedure is given to deduce large, small-signal and steady-state models from the unified signal flow graph of the converter. A straightforward algorithm is developed to draw the unified graph model of the N-cell cascade buck converter. The unified nature of the proposed method is discussed by taking illustrative examples. Converter performance expressions, small-signal transfer functions and steady state, are derived taking the two-cell buck converter as an example. A large-signal model is developed and has been programmed in a TUTSIM simulator. Large-signal responses against supply and load disturbances are obtained. The validity of the proposed signal flow graph modelling of the cascade buck converters is verified and compared through PSIM simulator results. A few experimental large-signal responses results are provided to verify the proposed method.

Signal flow graph modeling of two-cell cascade buck converters

This paper presents signal flow graph nonlinear modeling of two-cell cascade buck converters. A systematic procedure for developing the unified flow graph model of the cascade converter is discussed. A simplified procedure is described that can be used to deduce large, small-signal and steady-state models from the unified signal flow graph of the converter. Converter performance expressions, and small-signal and steady-state transfer functions are derived. The large-signal model is developed and programmed into a TUTSIM simulator. Converter large-signal responses are obtained against supply and load disturbances. The validity of the proposed signal flow graph modeling of cascade converters is verified and comparisons are made via PSIM simulator results. A few experimental results are provided to verify the proposed method.

General rules for signal flow graph modeling and analysis of DC-DC converters

Signal flow graph (SFG) nonlinear modeling approach is well known for modeling dc-dc converters. However, all possible SFGs of a given dc-dc converter system will not yield the generalized graph. A systematic procedure and guidelines for developing unified flow graph models of the dc-dc boost converters, from which complete behavior can be determined is presented. Usefulness of the proposed method is demonstrated through examples. As an illustration a 2-cell cascade boost and interleaved boost converter systems are taken as examples. Derivation of large, small-signal and steady-state models from generalized flow graph is also demonstrated. Large-signal model is developed and programmed in TUTSIM simulator. Large-signal, responses against supply and load disturbances are obtained. Experimental observations are provided to validate the proposed algorithm.

Signal flow graph modelling of multi-state boost DC–DC converters

A systematic procedure and guidelines for developing the unified flow graph model of a multi-state boost DC–DC converter is presented. From this unified model it is possible to predetermine the complete behaviour of the converter system. The proposed method provides ease of model formulation and avoids the mathematical complexity involved in obtaining the unified model. Usefulness of the proposed method is demonstrated through an example of three state boost converters. A simplified procedure is described that can be used to deduce large-signal, small-signal and steady-state from the unified signal flow graph of the converter. Large-signal models models have been developed and programmed in the TUTSIM simulator. Large-signal responses against supply and load disturbances were obtained. Theoretical results, obtained from the proposed signal flow graph method, are compared with PSIM power electronic simulator results. Experimental results are provided to validate the proposed modelling method.

Signal flow graph modelling of interleaved buck converters

AbstractThis paper presents a systematic development of unified signal flow graph model for an interleaved buck converter system operating in continuous inductor current mode. From this signal flow graph small, large‐signal and steady‐state models are developed, which are useful to study the converter dynamic and steady‐state behaviour. Converter performance expressions like steady‐state voltage gain, efficiency expressions and other small‐signal characteristic transfer functions are derived. Development of unified signal flow graph is explained for a 3‐cell interleaved converter system. Derivation of large, small‐signal and steady‐state models from the unified signal flow graph is demonstrated by considering a 2‐cell interleaved buck converter system. Large signal model was programmed in TUTSIM simulator, and the large‐signal responses against supply, load disturbances were predicted. Signal flow graph analysis results are validated with PSIM simulations. Further, the mathematical models obtained from the signal flow graph modelling are in agreement with those obtained from the state‐space averaging technique. Copyright © 2003 John Wiley &amp; Sons, Ltd.

Analysis of interleaved dual boost converter with integrated magnetics: signal flow graph approach

A systematic development of a unified signal flow graph model for an interleaved boost converter with coupled inductor system operating in continuous current mode is presented. This signal flow graph approach provides a means to directly translate the switching converter to its graphic model, from which steady-state and dynamic behaviour of the converter can easily be studied. Development of a unified signal flow graph is explained and derivation of large, small-signal and steady-state models is demonstrated. Converter performance expressions such as steady-state voltage gain, efficiency expressions and small-signal characteristic transfer functions are also derived. Large-signal responses against supply and load disturbances are predicted by programming the corresponding signal flow graph in the TUTSIM simulator. Experimental observations are provided to validate the signal flow graph modelling method. Frequency response characteristics generated from the signal flow method are validated with PSpice simulations. Further, the mathematical models obtained from the signal flow graph modelling are in agreement with those obtained from the state-space averaging technique.

Small‐signal analysis of interleaved dual boost converter

AbstractThis paper presents a systematic development of steady‐state, small‐signal models of interleaved dual boost converter operating in a continuous current mode. These models are derived by employing the well‐known signal flow graph method. This signal flow graph approach provides a means to directly translate the switching converter into its equivalent graphic model, from which a complete behaviour of the converter can easily be studied. Steady‐state performance, small‐signal characteristic transfer functions are derived using Mason's gain formula. The bode plots of audiosusceptibility, input impedance, output impedance, and control‐to‐output transfer functions are determined and illustrated using MATLAB for different values of load resistances, duty ratios. Small‐signal frequency responses obtained from the signal flow graph method are validated with PSPICE simulator results. To validate the signal flow graph modelling equations, sample steady‐state experimental results are provided. Copyright © 2001 John Wiley &amp; Sons, Ltd.

Signal flow graph modelling and analysis of interleaved DC?DC parallel converters

This paper presents a systematic development of a unified signal flow graph model for an interleaved DC–DC parallel converter system operating in continuous current mode. This signal flow graph approach provides a means to translate directly the switching converter to its graphic model, from which the steady-state and dynamic behaviour of the converter can be studied easily. The development of a unified signal flow graph is explained for a three-cell interleaved parallel converter system. Derivation of large-signal, small-signal and steady-state models from a unified signal flow graph is demonstrated by considering a two-cell interleaved converter system operating in complementary activation mode. Converter performance expressions such as steady-state voltage gain, efficiency expressions and small-signal characteristic transfer functions are also derived. A large-signal model was programmed in a TUTSIM simulator, and the large-signal responses against supply and load disturbances were predicted. Signal flow graph analysis results are validated with PSIM simulations. Experimental observations are provided to validate the signal flow graph modelling method. Further, the mathematical models obtained from the signal flow graph modelling are in agreement with those obtained from the state-space averaging technique.