SiGe Growth Research Articles

(Keynote) Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices

After a short description of the evolution of metal-oxide-semiconductor (MOS) device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material properties of complicated Si/SiGe multi-layer stacks used for complementary field effect transistor (CFET) devices. They contain two different Ge concentrations and have been grown using conventional process gases. A relatively high growth temperature is used to obtain acceptable Si and SiGe growth rates. Still island growth has been suppressed for Ge concentrations up to 40%. Excellent structural and optical material properties of the Si/SiGe multi-layer stack will be reported, with up to 3 + 3 Si channels in the top and bottom part of the stack, respectively. The absence/presence of lattice defects has been verified by room temperature photoluminescence measurements. Photoluminescence measurements at low temperatures are used to study band-to-band luminescence from individual sub-layers and to illustrate the optical material quality of the CFET stack.

Piezo Electric Properties of Epitaxial SiGe

Piezo resistivity of B- and P-doped epitaxial Si1-xGex (x=10-30%) is investigated to assess its application potential for thin film strain sensors. The gauge factor (GF) is calculated based on the change in resistivity to the externally induced compressive uniaxial strain along the current flow direction. In the case of B-doped SiGe, the resistivity decreases under the induced compressive strain which may be related to hole mobility enhancement, while no influence on the resistivity of the P-doped SiGe. A significant increase in the GF is observed by lowering B concentration. At the same B concentration, slightly higher GF is observed for higher Ge content. Moreover, the GF is slightly improved by lowering the SiGe growth temperature. The slight improvement may be related to improved crystallinity. These results suggest that the low-doped p-type SiGe deposited at low temperature has reasonable GF and can potentially be applied in strain sensors.

The Effects of Zone Volume and Gravity on Thermo-Solutal Marangoni Convection Instability in a Half-Zone Model of Float-Zone Growth of SiGe

The Effects of Zone Volume and Gravity on Thermo-Solutal Marangoni Convection Instability in a Half-Zone Model of Float-Zone Growth of SiGe

Thin and locally dislocation-free SiGe virtual substrate fabrication by lateral selective growth

Locally dislocation-free SiGe-on-insulator (SGOI) is fabricated by CVD. Lateral selective SiGe growth of ∼30%, ∼45% and ∼55% of Ge content is performed around ∼1 μm square Si(001) pillar located under the center of a 6.3 μm square SiO2 on Si-on-insulator substrate which is formed by H2-HCl vapor-phase etching. In the deposited SiGe layer, tensile strain is observed by top-view. The degree of strain is slightly increased at the corner of the SiGe. The tensile strain is caused by the partial compressive strain of SiGe in lateral direction and thermal expansion difference between Si and SiGe. Slightly higher Ge incorporation is observed in higher tensile strain region. At the peaks formed between the facets of growth front, Ge incorporation is reduced. These phenomena are pronounced for SiGe with higher Ge contents. Locally dislocation-free SGOI, which is beneficial for emerging device integration, is formed along 〈010〉 from the Si pillar by lateral aspect-ratio-trapping.

A study of iron-doped SiGe growth for thermoelectric applications

Silicon-germanium (SiGe) alloy has been studied for thermoelectric (TE) generators for decades due to its high-temperature stability. However, its low TE performance at a low temperature still needs to be solved. Nanoinclusion improves the TE performance, but the material and processing costs are still high. Here, we proposed a method by embedding silicide during crystal growth; in-situ observation at different cooling rates was carried out. At a 100 K/min cooling rate, a SiGe alloy containing α-FeSi2 precipitates was grown, which yielded a relatively low lattice thermal conductivity κlat of 4.80 Wm−1K−1 and a good zT value of 0.08 at room temperature. This was comparable to the commercial SiGe alloy, but the germanium used was reduced by 25%, and the process was much faster.

Lateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication

Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.

(G03 - Best Student Presentation Award) Lateral Selective SiGe Growth for Dislocation-Free Virtual Substrate Fabrication

SiGe virtual substrates (VS) having low-surface roughness with less defects are essential for fabricating emerging quantum devices such as qubits. Various techniques to grow VS are reported e.g. conventional graded buffers (1,2) and reverse graded buffers (3). However, these methods require several micrometer-thick buffer layers, having threading dislocations (TDs) network and develop crosshatch patterns resulting in high surface roughness, needing chemical mechanical polishing for planarization. In our previous work, lateral-selective Ge growth (4) was performed in a cavity formed by selective vapor phase etching (VPE) of Si from side of mesa-patterned SiO2 /Si structures fabricated on buried oxide (BOX) to create smooth and dislocation-free local Ge by horizontal aspect ratio trapping (ART). In this work, we demonstrate lateral-selective SiGe growth to realize smooth and dislocation-free local SiGe VS by lateral ART and discuss its surface morphology, strain and dislocations.Lateral-selective SiGe growth is done in a reduced-pressure chemical vapor deposition (RPCVD) system. Thermally oxidized silicon-on-insulator (SOI) wafers with 300 nm SiO2/300 nm Si/2 μm BOX are used. For the sample preparation, 6.3 μm square checkerboard SiO2/Si mesa structure with [110] oriented sidewalls is fabricated by photolithography patterning and reactive ion etching. After standard RCA cleaning followed by HF dip, the wafer is loaded into RPCVD reactor and pre-baked at 850oC in H2 to remove residual oxide. Thereafter, lateral HCl VPE of Si is performed at 850oC from side of mesa. Si pillar remains at center of the mesa. Then, SiGe is selectively deposited in the cavity around the Si pillar using a SiH2Cl2-GeH4-HCl gas mixture at 750oC. Finally, the top SiO2 is removed by HF. Atomic force microscopy (AFM) is used to measure the surface roughness. Energy dispersive X-Ray spectroscopy (EDX) is used for measuring Ge content distribution in SiGe. Micro-Raman spectroscopy is used to analyze strain distribution in Si and SiGe. Nano-beam diffraction (NBD) is employed for estimating the relative change of in- and out-of-plane SiGe lattice parameters. Plan-view transmission electron microscopy (TEM) is used for imaging dislocations.Fig. 1 shows the AFM image for surface morphology of lateral-selective Si0.6Ge0.4 around the Si pillar. SiGe has root mean square roughness of ~0.16 nm, which is similar to blanket Si(001) (~0.14 nm), because the SiGe surface roughness is determined by interface roughness of top SiO2 and sacrificially etched Si. Uniform Ge content of ~40% in SiGe layer is observed by EDX analysis (Fig. 2). In the Si pillar part of Fig. 3, relative uniform tensile-strain of ~0.4% is observed. Since Si is negligibly strained in unpatterned area of SOI (taken as reference), hence during HCl VPE at 850oC, Si pillar/SiO2 interface could slip by higher thermal expansion of Si as interface decreases. Tensile-strain in Si pillar could be formed during cooling process. Ideally, ~1.68% lattice mismatch strain should exist in fully-relaxed ~40% SiGe on Si. However, higher tensile-strain (~2.5%) in SiGe is observed at corners along [010]. To clarify the reason of higher strain at corners, in- and out-of-plane SiGe lattice parameters near Si pillar (as marked in Fig 4(a)) are investigated by NBD. Higher in-plane lattice parameter in [110] is observed in the edge part of the SiGe lamella as compared to the center part (Fig. 4(b)). However, out-of-plane lattice parameter in [001] is homogeneous across entire SiGe (Fig. 4(c)). Because SiGe has uniform Ge concentration as shown in Fig. 2, higher lattice parameter in the edge part of Fig. 4(b) is caused by strain difference. This is because SiGe lamella edge (away from Si pillar) is more relaxed as compared to SiGe lamella center (beside Si pillar) which is confirmed by vertically grown ~700 nm 40% SiGe on blanket Si(110). Symmetric strain distribution does also exist in 90° rotated direction. Therefore, the tensile-strain in [010] is induced from both [110] and [-110]. In Fig. 5, stacking faults of SiGe on (111) plane are observed along [110] and [1-10]. TDs are present along [111], terminated by top SiO2/BOX and located up to first ~400 nm from Si while misfit dislocations are at Si/SiGe interface. Wide dislocation-free area in SiGe is present along [010].This technique enables dislocation-free local SiGe-on-insulator substrate fabrication which can be applied for thin and high quality VS for the quantum devices. References E. A. Fitzgerald et al., J. Appl. Phys., 63, 693 (1988).E. A. Fitzgerald et al., Appl. Phys. Lett., 59, 811 (1991).V. A. Shah et al., Appl. Phys. Lett., 93, 192103 (2008).Y. Yamamoto et al., ECS J. of Solid State Sci. and Technol., 3, 353 (2014). Figure 1

(Best Student Presentation Award) Reduced Pressure – Chemical Vapor Deposition of Monocrystalline and Polycrystalline Si(:B) and SiGe(:B) Layers on Blanket Wafers

Monocrystalline SiGe alloys can be used instead of monocrystalline Si in order to increase the performances of devices such as heterojunction bipolar transistors (HBTs) [1]. The epitaxial growth of blanket, monocrystalline SiGe layers on Si with a dichlorosilane + germane + hydrochloric acid chemistry was extensively investigated in the literature [2,3]. Similarly, a switch from polycrystalline Si to polycrystalline SiGe can be favorable, for instance, in Complementary-MOS (C-MOS) devices [4,5]. However, the blanket growth by Reduced-Pressure Vapor Deposition (RP-CVD) of polycrystalline Si and SiGe has not been systematically investigated. We have thus performed a one-to-one comparison in terms of growth kinetics and electrically active dopant incorporation between blanket monocrystalline and polycrystalline Si(:B) and SiGe(:B) layers.Epitaxies or depositions were performed, in 300 mm RP-CVD chambers, on two types of templates (Fig.1): i) N-type Si substrates (Fig.1(a)) and ii) poly-Si/oxide/ P-type Si substrates (Fig.1(b)). The poly-Si layer in stack 1.(b) was obtained thanks to amorphous Si deposition followed by annealing at 750 °C, resulting in a poly-Si film. SiH4+HCl+H2 (named Process 1) and SiH2Cl2 (DCS)+HCl+GeH4+H2 (named Process 2) chemistries were used to deposit Si and SiGe layers between 675-750 °C and 10-20 Torr.Monocrystalline and polycrystalline SiGe growth kinetics for two process conditions: i) 750 °C, 10 Torr with a HCl partial pressure of 0.05 Torr and ii) 725 °C, 10 Torr, with a HCl partial pressure of 0.06 Torr, were similar to that in the literature [1-3, 6-8]. As already shown for monocrystalline layers, there was an increase of the intrinsic SiGe growth with the germane partial pressure and the temperature. Meanwhile, it was reduced when adding HCl (Fig.2). Very similar growth rates and evolutions were however obtained whatever the crystalline state of the layers.When diborane was added the gaseous mixture, different behaviors were evidenced depending on i) the crystallinity and ii) the stoichiometry. The Si:B and SiGe:B growth rates increased with the B2H6 flow whatever the chemistry (Fig.3). This was due to a hydrogen desorption increase on boron surface sites [5,10-11]. Growth rates were otherwise higher for monocrystalline than for polycrystalline layers. The electrical resistivities of c-Si:B and c-SiGe:B layers were one decade lower than those of poly-Si:B and poly-SiGe:B layers, however (Fig.4). Resistivity values were otherwise higher for c-Si:B than for c-SiGe:B. This was likely due to i) a better incorporation of B atoms into SiGe than in Si [3,8,9] and ii) a better hole mobility in SiGe [10]. An opposite behavior was observed for polycrystalline layers, with higher resistivities for poly-SiGe:B than for poly-Si:B. We otherwise had similar resistivity evolutions as the partial pressure of diborane Pp(B2H6) increased for all types of layers. A decrease was observed first, followed by a resistivity plateau then some resistivity re-increase for really high diborane flows. Such a phenomenon was already observed for monocrystalline layers and was explained by a crystalline quality degradation [3,8,9] that reduced the hole mobility. A similar behavior was assumed for poly-layers, with a morphological transition to the amorphous phase [11,12]. Top-view Scanning Electron Microscopy (SEM) images (Fig. 5) confirmed the morphological evolution of c-Si:B, poly-Si:B, c-SiGe:B and poly-SiGe:B as the diborane partial pressure increased.New data points for c-SiGe and c-SiGe:B will also be provided for other process conditions. For intrinsic layers, we will show that Refs. [1,2] x2/(1-x) = n×(F(GeH4)/F(SiH2Cl2)) relationship between the Ge concentration x and the germane over dichlorosilane mass-flow ratio is also valid at 10 Torr, with n = 3 at 700 °C with a F(SiH2Cl2)/F(H2) Mass-Flow Ratio (MFR) of 0.005 and a F(HCl)/F(H2) MFR of 0.006. Various characterization techniques were also used to determine the concentration of substitutional Boron atoms in SiGe:B layers and the lattice contraction coefficient (β = 9.11×10-24 cm3). The value of the latter, which is most useful to assess the compressive strain compensation by small boron atoms in SiGe layers, will be compared to literature values.[1] J. Appl. Phys. 88 (2000) 4044[2] J. Crystal Growth 305 (2007) 113[3] J. Crystal Growth 310 (2008) 62[4] J. Microelec. Sys. 16 (2007) 68[5] International Electron Devices Meeting (1991) 567[6] Appl. Phys. Lett. 56 (1990) 1275.[7] S. Chang et al., ECS Proceedings 87–8 (1987) 122[8] J Mater Sci: Mater Electron (2007) 18:747[9] ECS Trans. 75, 8 (2016) 265[10] Mater. Sci. Eng. B 114–115 (2004) 318[11] Appl. Phys. Lett. 66 (1995) 195[12] ECS Trans. 35, 30 (2011) 45 Figure 1

(Digital Presentation) Epitaxially Grown of SiGe on Ge Microbridge and Observation of Strong Resonant Light Emission

Introduction Ge has been attracting attention for the realization of intra chip optical integrated circuits. In particular, the introduction of tensile strain by epitaxial growth of Ge on Si substrate improves the direct transition probability by shifting the Γ-valley, resulting in an increase in luminescence efficiency. Furthermore, by forming Ge microbridge structure, the larger uniaxial tensile strain can be induced into the freestanding Ge, which is expected to further improve the luminescence efficiency [1]. However, when the stronger tensile strain is applied to Ge, the emission wavelength shifts significantly to the longer wavelength. In order to arbitrary control the emission wavelength to the shorter, especially within the telecommunication wavelength band, introduction of SiGe/Ge heterostructures in the microbridge is considered to be one of the most proper ways. In this work, we attempt to grow the strained SiGe layer on the Ge microbridge and observe the shorter wavelength light emission from the strained SiGe. Moreover, it has been shown that Fabry-Perot resonance takes place in the Ge microbridge structure owing to the side wall reflection [2], leading to the strong resonant luminescence peaks. Here also we observe the resonant light emission from the SiGe/Ge microbridge structure. Experimental Methods A Ge layer was grown on a Si(100) wafer by solid-source molecular beam epitaxy (MBE) with using so-called two-step growth method. First, a 40-nm-thick buffer layer was grown at a low temperature of 350 °C. Then, 500 nm thick Ge layer was grown at 600 °C. Finally, thermal annealing was performed in situ at a temperature of 800 °C for 10 min to reduce the threading dislocation density in Ge layers. After the MBE growth, patterning of the microbridge structure was performed by standard photolithography process and inductively coupled plasma reactive-ion dry etching. Si beneath the microbridge was then removed to form freestanding structures by KOH wet etching. After fabrication of the Ge microbridge, 60 nm thick Si0.2Ge0.8 layer was directly grown on the Ge microbridge at 350 °C. Results and Discussion SEM observation showed that fine microbridge structure remains unchanged after the Si0.2Ge0.8 layer overgrowth on the Ge microbridge. Raman measurements confirmed that the grown SiGe has tensile strain originated from the lattice mismatch between the Si0.2Ge0.8 and underneath Ge, indicating that elastic strain relaxation did not occur. A PL spectrum obtained from the central position of the Si0.2Ge0.8 microbridge exhibits strong light emission in the wavelength range from 1500 to 2000 nm. This is thought to be originated both from SiGe and Ge layers. The PL intensity around shorter wavelength region is significantly increased after the Si0.2Ge0.8 epitaxial growth compared to that before the growth, indicating that the SiGe growth is contributing to the light emission at the telecommunication band. It is noted that a PL spectrum obtained in the unpatterned area from the same sample has almost no light emission, indicating that the microbridge structure is very promising for obtaining the strong light emission. Also it is remarkable that the resonance peaks can be obviously observed. The calculation confirmed this resonance is due to the reflection between side walls of the microbridge. From these results, we can say that the SiGe/Ge heterostructure based microbriges serve as wavelength-controllable high efficiency light sources on Si.This work was partially supported by JSPS KAKENHI (Nos. 19H02175, 19H05616 and 20K21009).[1] M. J. Suess et al, Nat. Photonics 7: 466, 2013[2] Peiji Zhou et al 2018 Jpn. J. Appl. Phys. 57 04FH10 Figure 1

Low Temperature Epitaxy of In Situ GaDoped Si1-XGex: Dopant Incorporation, Structural and Electrical Properties

Over the last few decades, MOSFET architectures have evolved from planar to 3D structures (FinFET and, more recently, gate-all-around and Forksheet devices) to improve the channel control at very scaled dimensions. In this framework, highly doped conformal Si1-xGex epitaxial films are used for source/drain (S/D) regions in pMOS devices to form ohmic metal-semiconductor contacts with low specific contact resistivities (ρc). Boron is the main p-type dopant in Si1-xGex thanks to its high active concentration (~ 1×1021 at./cm3) for Ge concentrations of ~ 50 at.% [1]. For higher Ge/Si ratios, gallium is considered a promising doping element due to its higher solid solubility in Ge compared with boron. However, a strong Ga surface segregation is reported to occur during the epitaxy of in situ doped Si1-xGex, leading to a Ga-rich second phase at the epilayer surface [2]. In films grown at temperatures ≥ 450°C, the Ga surface segregation limits the bulk Ga concentration ([Ga]chem) to 1×1018 at./cm3 [3]. This low doping level results in inferior electrical properties for current MOSFET applications. Models in the literature [4] indicate that, at sufficiently low temperature, dopant segregation is limited by surface kinetic mechanisms. Thus, the segregation ratio could be controlled by changing the process temperature. Based on this approach, low temperature, Si2H6 + Ge2H6 based processes with improved Ga incorporation were developed [5].In this contribution, we report on novel in situ Ga doped Si1-xGex epitaxial layers grown at temperatures ≤ 400°C. Using a HCl surface clean, necessary to avoid the SIMS Ga decay from the surface which can mask the real concentration profile [3], Ga box-shaped profiles with concentrations above 1×1020 at./cm3 are found (Fig. 1). Two growth temperatures are compared: 400°C and 350°C. For each temperature, variable Ga precursor (tri-tert-butyl gallium) flows (fTTBGa) were used. A reduction in the growth temperature enhances the Ga incorporation, as evidenced from the two SEM morphology inspections displayed in Fig. 1. Here, two samples with a similar bulk [Ga]chem of ~ 6 ×1019 at./cm3, as measured by SIMS, exhibit either a clustered or smooth surface depending on the deposition temperature applied.This improved Ga incorporation allows for systematic studies of in situ Ga doping on the structural and electrical properties of Si1-xGex. In both series of samples, the layer resistivities (ρ) follow a similar trend, characterized by a steep decrease at smaller fTTBGa and a plateau for higher flows (Fig. 2). The lowest ρ values are found for the layers grown at 350°C. This denotes that different saturation levels in the active Ga concentration ([Ga]act) exist for the process conditions used here. In a similar way to what is typically observed for B doping, an increase in the Ga doping level causes a boost in epilayer growth rate. This growth rate trend saturates simultaneously with ρ, suggesting that the phenomenon is linked to the level of incorporated substitutional Ga atoms. In addition, the resulting Ge concentrations of the Si1-xGex layers are found to increase with Ga concentration. From HR-XRD analysis, strain-relaxation is also found to progressively increase with the TTBGa flow and so the incorporated Ga may not be fully active. For this reason, X-ray absorption fine structure spectra (XAFS) were acquired at the Ga K-edge on Si0.4Ge0.6:Ga and Ge:Ga epilayers with the results obtained reported in Fig.3. Based on comparative analysis of the first coordination Ga shell with DFT simulation results, Ga dopants appear to be placed in substitutional positions for both materials. Furthermore, a shorter nearest-neighbors distance is measured for Ga in Si0.4Ge0.6 compared to Ge, indicating a difference in the local strain associated to the dopant for the two considered matrixes.[1] R. Loo et al., “Processing Technologies for Advanced Ge Devices,” ECS J. Solid State Sci. Technol., vol. 6, no. 1, pp. P14–P20, 2017.[2] J. Margetis et al., “Epitaxial Growth of Ga-doped SiGe for Reduction of Contact Resistance in finFET Source/Drain Materials,” ECS Trans., vol. 93, no. 1, pp. 7–10, 2019.[3] G. Rengo et al., “B and Ga Co-Doped Si1−xGex for p-Type Source/Drain Contacts,” ECS J. Solid State Sci. Technol., vol. 11, no. 2, 024008, 2022.[4] C. B. Arnold and M. J. Aziz, “Unified kinetic model of dopant segregation during vapor-phase growth,” Phys. Rev. B - Condens. Matter Mater. Phys., vol. 72, no. 19, 195419, 2005.[5] A. Y. Hikavyy et al., “Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts,” ECS Trans., vol. 104, no. 4, pp. 139–146, Oct. 2021. Figure 1

Substitutional Carbon Incorporation in SiGeC/Si Heterostructures: Influence of Silicon Precursors

The incorporation of germanium and carbon by RP-CVD epitaxy in silicon brings lots of interest in silicon devices thanks to the variety of properties that can be addressed: band gap or lattice parameter engineering, dopant diffusion reduction, chemical properties, optical properties...For all the applications requiring SiGeC materials, carbon atoms must be incorporated in fully substitutional site (Cs) despite its low bulk solubility into the Si and SiGe lattice (3x1017 at.cm-3 at the Si melting point). Beyond a total carbon concentration (depending on process parameter), carbon atoms are also incorporated into interstitial sites (Ci). These Ci atoms usually form extended defects such as clusters or SiC precipitates which are harmful for devices performances.Solubility limits of carbon can be extended into the metastable domain by optimizing the epitaxy process. Indeed, it is well established that low temperature and high growth rate are favorable to obtain high Cs atoms incorporation [1].This work compares silane (SiH4) and disilane (Si2H6) precursors coupled with germane (GeH4) and methylsilane (SiH3CH3 or MS) to process low temperature thin film of SiGeC with the highest amount of Cs without Ci.First, the SiGe growth kinetics using silane and disilane have been studied. The temperature range investigated varied from 500 °C to 600 °C at low pressure. Using similar atomic fluxes of Si, and with all the other parameters constant, a higher growth rate and lower germanium content has been observed with disilane compared to silane. For instance, there is a factor of 1.85 at 550°C. The germanium concentration was varying from 30.4 to 22.3 % and from 19.4 to 15.7 % for silane and disilane, respectively. To have a better understanding about this kinetics difference, an impoverishment rate or theoretical yield, of the gas phase, in reactive species has been calculated. The hypothesis is that the impoverishment rate is linked to the reactivity of a molecule, and thus related to the sticking probability of a molecule onto a same surface [2].The impoverishment rate is defined as the ratio between the number of moles of Si (or Ge) deposited per minute (nDeposited) and the number of moles of silicon precursor (or germanium) injected per minute(nInjected) in the epitaxy reactor: αPrecursor = nDeposited/nInjected. The impoverishment rate of the disilane molecule increases much more rapidly than the silane molecule as the temperature increases (Fig.1a). Disilane is more consumed than silane which is relevant of the higher reactivity of disilane compared to silane.Moreover, the impoverishment of germane increases more rapidly with disilane than with silane (Fig.1b). The GeH4 contribution to epitaxy is more significant using disilane than silane. The impoverishment rate of precursors according to the germane flow will be presented later.Then, silane and disilane precursors have been compared with respect to the C incorporation at 550 °C. Ge concentration was fixed to 20 % with both silicon precursors. This leads to a growth rate of SiGe equal to 2.9 and 14.1 nm.min-1 using silane and disilane, respectively. XRD has been used to gain access to the “apparent” Ge concentration in Si1-x-yGexCy layers (Fig.2(a), (b)). Carbon atoms, much smaller than silicon and germanium, compensate the compressive strain induced by germanium in the SiGe layers. It then yields smaller Ge concentration in XRD than the real Ge concentration. The carbon in substitutional position can therefore be extracted using this coefficient: 1 % of carbon compensate 12 % of Ge [3].Using disilane, the substitutional carbon concentration linearly increases with the MS flow over the whole studied range (Fig.3). However, using silane, a deviation from the linearity is observed (above 0.7 %). In the linearity part of the curves, all the carbon incorporated are in substitutional site (as the total amount of carbon atoms increasing linearly with the MS flow [4]). When a non-linearity occurs, C atoms started to be incorporated in interstitial position also. SIMS measurement will be performed to confirm that. At 550 °C, the growth rate of SiGe is more important with disilane precursor due its higher reactivity than silane. Its leads to a better substitutional carbon incorporation. Indeed, using disilane, up to 1.15 % of fully substitutional carbon can be reached while using silane, only 0.7 % is reached.[1] V. Loup et al., J. Vac. Sci. Technol. B 21(1), Jan/Feb 2003.[2] D.J. Robbins et al., Journal of Applied Physics 69, 3729 (1991).[3] D. De Salvador et al., Phys. Rev. B, vol. 61, pp. 13005, 2000.[4] V. Loup et al., J. Vac. Sci. Technol. B 20(3), May/Jun 2002. Figure 1

Lateral Selective SiGe Growth for Dislocation-Free Virtual Substrate Fabrication

Dislocation free local SiGe-on-insulator virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 µm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2 / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ~1.4% along <010> direction, which is higher compared to that along <110> direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards <110> directions, resulting in wide dislocation-free area formation in SiGe along <010> due to horizontal aspect ratio trapping.

Substitutional Carbon Incorporation in SiGeC/Si Heterostructures: Influence of Silicon Precursors

In this paper, SiGe or SiGeC epitaxy with Silane or Disilane, Germane and Methylsilane precursors was studied in a 300 mm industrial Reduced Pressure-Chemical Vapor Deposition (RP-CVD) reactor. The SiGe growth rate exponentially increased with the temperature in the 500 °C - 600 °C range for both silicon precursors (activation energy Ea = 2.1 eV). It was, at 550 °C, almost twice higher with Si2H6 than with SiH4. At low temperature, Si2H6 is indeed more reactive than SiH4, resulting in SiGe growth rates significantly higher for a given germanium composition. Then, carbon incorporation at 550 °C into Si0.8Ge0.2 was studied. The higher reactivity of Si2H6 compared to SiH4 resulted in a better substitutional carbon incorporation. In our experimental conditions, 1.2 at% of fully substitutional carbon atoms could indeed be obtained with Si2H6 (without any detectable interstitial ones). Meanwhile, only 0.5 at% of fully substitutional carbon atoms was obtained with SiH4.

Epitaxial growth of SiGe films by annealing Al–Ge alloyed pastes on Si substrate

A simple, low-cost, and non-vacuum epitaxial growth method to realize large-area semiconductors on crystalline silicon will become the game-changer for various applications. For example, we can expect the disruptive effect on the cost of large-scale III–V multi-junction solar cells if we could replace the high-cost germanium substrate with silicon–germanium (SiGe) on Si. For SiGe epitaxial growth, we attempted to develop a process using original Al–Ge pastes for screen printing and subsequent annealing. We compare two pastes including Al–Ge alloyed pastes with compositional uniformity in each particle and Al–Ge mixed pastes. We revealed that Al–Ge alloyed paste could form flatter SiGe film with much less residual pastes, supported by in-situ observations. The uniform and sufficient dissolution of the alloyed paste is responsible for these and led to higher average Ge-composition by annealing at 500 °C. The composition in SiGe was vertically graded up to ~ 90% at the topmost surface. These results show that printing and firing of Al–Ge alloyed paste on Si is the desirable, simple, and high-speed process for epitaxial growth of SiGe, which could be potentially used as the lattice-matched virtual substrate with III–V semiconductors.

Increased Critical Thickness for Strained SiGe on Ge-on-Si(111)

Since a Ge has been recognized as one of the promising alternative materials to Si, many researches have been pursued mostly based on a bulk Ge with a (100) surface orientation. Recently, it has been shown that a Ge with a (111) orientation is more favorable for applications to spintronics devices because high quality ferromagnetic materials can be epitaxially grown on the Ge(111)[1]. Also a strained SiGe(111) is expected to improve the spin lifetime of electrons. So far, however, epitaxial growth of tensile-strained SiGe on Ge has not been explored sufficiently.Recently we systematically investigated critical thickness of the strained SiGe/Ge-on-Si(111) [2], and found that unusual line-shaped ridge roughness appears on the SiGe surface at the initial stage of strain relaxation. Moreover, we observed generation of cracks extending deep into underlying Ge layer in the ridge region, imposing essential requirements to suppress the formation of cracks and related ridges. For this purpose, we attempted the growth of a strained SiGe on a Ge-on-Si(111) that was patterned in line & space mesa and succeeded in suppression of the ridge roughness formation [3]. Toward device applications, such as spintronics devices, we need to widen the area of the crack-free strained SiGe and to increase critical thickness of the strained SiGe/Ge-on-Si.In this work, we employ much larger (~ 50 um) square-shaped mesa-pattern of the Ge-on-Si and succeed in the growth of crack-free strained SiGe with the thickness which largely exceeds the expected critical thickness.In experiments, the crystal growth was carried out with solid source molecular beam epitaxy. The Ge-on-Si(111) was fabricated using the so-called two-step growth method. The 40 and 650 nm thick Ge layers were subsequently grown on a Si(111) substrate at 400 and 700 °C, respectively, followed by annealing at 800 °C for 10 min. For experiments of the SiGe growth on the patterned Ge(111) and Ge-on-Si(111), one of the Ge(111) samples and grown Ge-on-Si(111) samples was subjected to photolithography process[3]. Subsequently the 200 to 250 nm thick SiGe layer was grown on the patterned Ge(111) and Ge-on-Si(111) substrate at 350 °C.Figures 1(a)-1(d) show laser microscope (LM) surface images of 200 or 250 nm thick strained SiGe layers grown on (a) the un-patterned Ge-on-Si(111), (b) the patterned Ge-on-Si(111), (c) the un-patterned Ge(111) substrate and (d) patterned Ge(111) substrate. For the 250 nm thick Si0.2Ge0.8 on the un-patterned GOS [Fig. 1(a)], we can clearly observe high-density ridge roughness running along three equivalent [1-10], [10-1] and [01-1] directions, which are corresponding to intersections of surface and (111) slip planes. The ridge roughness involves cracks along the plane. In contrast, for the 250 nm thick Si0.2Ge0.8 on the patterned GOS [Fig. 1(b)], we can find the surface is very flat without such ridge roughness. This result implies that the strain energy accommodated in the strained SiGe is effectively released at mesa edges, which can eliminate a driving force for the ridge roughness formation, that is, the crack formation. It is very interesting to compare these results with those obtained for the SiGe on Ge substrates. Figs. 1(c) and (d) shows ridge roughness appears for both 200 nm thick SiGe layers grown on the patterned and un-patterned Ge(111) substrates. This means that the patterning cannot suppress the ridge formation for the case of the strained SiGe on the Ge(111) substrate. Note that the ridge roughness is seen to be connected between the mesa patterned and etched areas, implying that the SiGe film grown on the etched area affects the ridge formation mechanism.In conclusion, we can say that the critical thickness of the strained SiGe can be significantly increased by means of growing the SiGe layer on the patterned Ge-on-Si(111) and the 250 nm thick strained Si0.2Ge0.8 can be grown without any roughness and crack formation. This thickness largely exceeds an expected critical thickness for the Si0.2Ge0.8/Ge(111) [2]. It can be said that this method can highly widen the applicability of the strained SiGe(111) heterostructures to spintronics and high performance electronic devices.This work was supported in part by MEXT Supported Program for theStrategic Research Foundation at Private Universities 2015–2019 and by Grant-in-Aid for Scientific Research (Nos. 16H02333, 19H02175 and 19H05616) from MEXT, Japan[1] K. Hamaya et al., J. Phys. D: Appl. Phys. 51, 393001 (2018).[2] Md. M. Alam et al., Appl. Phys. Express 12, 081005 (2019).[3] Y. Wagatsuma et al., Mater. Sci. Semicond. Process. 117, 105153 (2020). Figure 1

Very low temperature growth of GeSi alloys with digermane, disilane and dichlorosilane

GeSn/GeSi multi quantum wells with (i) high Sn content, direct bandgap GeSn wells and (ii) GeSi barriers with Si contents in the few %–30% range might be of use in optoelectronics. As GeSn has to be grown in the 300–375 °C range (to avoid Sn segregation/precipitation), GeSi barriers should also be grown in that temperature range, too. GeSi might also be used to passivate, at low temperatures, the surface of Ge-rich imagers and photo-detectors. Thanks to X-Ray Reflectivity (thickness) and X-Ray Diffraction (Si content), I have therefore explored, in a 200 mm Chemical Vapour Deposition tool, the 100 Torr growth of tens of nm thick GeSi layers on Ge(001) buffers. Precursor gases were Ge2H6 (Ge), SiH2Cl2 and/or Si2H6 (Si). Whatever the chemistry, a temperature increase in the 350–500 °C range resulted in an increase, (a stabilization) then a decrease of the GeSi growth rate. Meanwhile, the Si content increased almost linearly with the temperature. For given Si and Ge flows, GeSi growth rates were higher and Si contents lower with SiH2Cl2 than with Si2H6. Adding SiH2Cl2 to Si2H6 had, quite surprisingly, almost no impact on the GeSi growth kinetics, which was mainly governed by the Si2H6 flow. With high precursor flows, I succeeded in having, with Ge2H6 and SiH2Cl2, GeSi growth rates increasing from 2 up to 32 nm min−1 as the temperature increased from 325 °C up to 375 °C, with a Si content close to 7.5%. Growth rates increased from 0.6 up to 19 nm min−1 and Si contents decreased from 24 down to 22% over the same temperature range with Ge2H6, SiH2Cl2 and Si2H6.

Epitaxial Growth of Ga-doped SiGe for Reduction of Contact Resistance in finFET Source/Drain Materials

Here we evaluate in-situ Ga doping of SiGe as an alternative to ex-situ ion implantation for source/drain contact formation. Si0.5Ge0.5 layers are grown on an ASM Intrepid ES high volume CVD reactor and co-doped with B and Ga. A circular transmission line measurement (CTLM) comparison of SiGe:B and SiGe:B:Ga is presented and we report a statistically significant improvement in contact resistivity with the addition of Ga. The Ti/SiGe contacts formed with the B-doped sample had an average ρc ~ 9 x 10-9 Ω-cm2 while the best Ga/B co-doped sample yielded an average ρc ~ 2.5 x 10-9 Ω-cm2. We also evaluate the epitaxial growth on fin patterned wafers and we are able to demonstrate high crystalline quality SiGe:Ga layers without loss of selectivity on the dielectric areas of the wafer.

SiGe quantum well infrared photodetectors on strained-silicon-on-insulator.

We demonstrate p-type SiGe quantum well infrared photodetectors (QWIPs) on a strained-silicon-on-insulator (sSOI) substrate. The sSOI system allows strain-balancing between the QWIP heterostructure with an average composition of Si0.7Ge0.3 and the substrate, and therefore lifts restrictions to the active material thickness faced by SiGe growth on silicon or silicon-on-insulator substrates. The realized sSOI QWIPs feature a responsivity peak at detection wavelengths around 6 µm, based on a transition between heavy-hole states. The fabricated devices have been thoroughly characterized and compared to equivalent material simultaneously grown on virtual Si0.7Ge0.3 substrates based on graded SiGe buffers. Responsivities of up to 3.6 mA/W are achieved by the sSOI QWIPs at 77 K, demonstrating the large potential of sSOI-based devices as components for a group-IV optoelectronic platform in the mid-infrared spectral region.

Epitaxial growth of SiGe on Si substrate by printing and firing of Al–Ge mixed paste

We report on a simple liquid-phase epitaxy (LPE) of SiGe on Si (100) substrate based on printing and firing. LPE was performed using an Al–Ge mixed paste screen-printed on a Si (100) substrate followed by annealing above the Al–Ge eutectic temperature in air or in an Ar atmosphere. In the case of annealing in air at 800 °C, SiGe was formed between the mixed paste and the surface of the Si substrate. However, a wave-like oxide film was confirmed at the SiGe/Si interface, which hindered the growth of SiGe. On the other hand, annealing in the Ar atmosphere at 800 °C led to the successful formation of a more continuous, thicker SiGe film by suppressing the oxidation of Al. It can be concluded that LPE growth using printing and firing of Al–Ge mixed paste is a suitable method to grow SiGe with a low-cost and simple high-speed process.

Optimization and Scaling of Ge-Pocket TFET

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage ( ${V} _{\textsf {DD}}$ ). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current ( ${I} _{\textsf {on}}$ ) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length ( ${L} _{\textsf {gate}}$ ) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications.