Low Temperature Epitaxy of In Situ GaDoped Si1-XGex: Dopant Incorporation, Structural and Electrical Properties

Abstract

Over the last few decades, MOSFET architectures have evolved from planar to 3D structures (FinFET and, more recently, gate-all-around and Forksheet devices) to improve the channel control at very scaled dimensions. In this framework, highly doped conformal Si1-xGex epitaxial films are used for source/drain (S/D) regions in pMOS devices to form ohmic metal-semiconductor contacts with low specific contact resistivities (ρc). Boron is the main p-type dopant in Si1-xGex thanks to its high active concentration (~ 1×1021 at./cm3) for Ge concentrations of ~ 50 at.% [1]. For higher Ge/Si ratios, gallium is considered a promising doping element due to its higher solid solubility in Ge compared with boron. However, a strong Ga surface segregation is reported to occur during the epitaxy of in situ doped Si1-xGex, leading to a Ga-rich second phase at the epilayer surface [2]. In films grown at temperatures ≥ 450°C, the Ga surface segregation limits the bulk Ga concentration ([Ga]chem) to 1×1018 at./cm3 [3]. This low doping level results in inferior electrical properties for current MOSFET applications. Models in the literature [4] indicate that, at sufficiently low temperature, dopant segregation is limited by surface kinetic mechanisms. Thus, the segregation ratio could be controlled by changing the process temperature. Based on this approach, low temperature, Si2H6 + Ge2H6 based processes with improved Ga incorporation were developed [5].In this contribution, we report on novel in situ Ga doped Si1-xGex epitaxial layers grown at temperatures ≤ 400°C. Using a HCl surface clean, necessary to avoid the SIMS Ga decay from the surface which can mask the real concentration profile [3], Ga box-shaped profiles with concentrations above 1×1020 at./cm3 are found (Fig. 1). Two growth temperatures are compared: 400°C and 350°C. For each temperature, variable Ga precursor (tri-tert-butyl gallium) flows (fTTBGa) were used. A reduction in the growth temperature enhances the Ga incorporation, as evidenced from the two SEM morphology inspections displayed in Fig. 1. Here, two samples with a similar bulk [Ga]chem of ~ 6 ×1019 at./cm3, as measured by SIMS, exhibit either a clustered or smooth surface depending on the deposition temperature applied.This improved Ga incorporation allows for systematic studies of in situ Ga doping on the structural and electrical properties of Si1-xGex. In both series of samples, the layer resistivities (ρ) follow a similar trend, characterized by a steep decrease at smaller fTTBGa and a plateau for higher flows (Fig. 2). The lowest ρ values are found for the layers grown at 350°C. This denotes that different saturation levels in the active Ga concentration ([Ga]act) exist for the process conditions used here. In a similar way to what is typically observed for B doping, an increase in the Ga doping level causes a boost in epilayer growth rate. This growth rate trend saturates simultaneously with ρ, suggesting that the phenomenon is linked to the level of incorporated substitutional Ga atoms. In addition, the resulting Ge concentrations of the Si1-xGex layers are found to increase with Ga concentration. From HR-XRD analysis, strain-relaxation is also found to progressively increase with the TTBGa flow and so the incorporated Ga may not be fully active. For this reason, X-ray absorption fine structure spectra (XAFS) were acquired at the Ga K-edge on Si0.4Ge0.6:Ga and Ge:Ga epilayers with the results obtained reported in Fig.3. Based on comparative analysis of the first coordination Ga shell with DFT simulation results, Ga dopants appear to be placed in substitutional positions for both materials. Furthermore, a shorter nearest-neighbors distance is measured for Ga in Si0.4Ge0.6 compared to Ge, indicating a difference in the local strain associated to the dopant for the two considered matrixes.[1] R. Loo et al., “Processing Technologies for Advanced Ge Devices,” ECS J. Solid State Sci. Technol., vol. 6, no. 1, pp. P14–P20, 2017.[2] J. Margetis et al., “Epitaxial Growth of Ga-doped SiGe for Reduction of Contact Resistance in finFET Source/Drain Materials,” ECS Trans., vol. 93, no. 1, pp. 7–10, 2019.[3] G. Rengo et al., “B and Ga Co-Doped Si1−xGex for p-Type Source/Drain Contacts,” ECS J. Solid State Sci. Technol., vol. 11, no. 2, 024008, 2022.[4] C. B. Arnold and M. J. Aziz, “Unified kinetic model of dopant segregation during vapor-phase growth,” Phys. Rev. B - Condens. Matter Mater. Phys., vol. 72, no. 19, 195419, 2005.[5] A. Y. Hikavyy et al., “Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts,” ECS Trans., vol. 104, no. 4, pp. 139–146, Oct. 2021. Figure 1