Sidewall Image Transfer Research Articles

Atomic Layer Deposition of Sidewall Spacers: Process, Equipment and Integration Challenges in State-of-the-Art Logic Technologies

Dielectric thin film spacers play a very important role in defining the silicon channel boundary and junction geometries as well as proximity to silicon stressors and strongly affect key transistor electrical characteristics [1]. Another important application of sidewall spacers is in patterning of 3D FinFETs (Field Effect Transistor), where the Sidewall Image Transfer (SIT) technology [2] helps to overcome the limitations of conventional lithography and to improve control of critical dimensions. Sidewall spacers are also used to control critical dimension (CD) by depositing a spacer film inside a feature to achieve a CD shrink. Tolerance for variability of TFin(Fin width) has to be in the sub nm range to significantly reduce variability in FinFET performance. The need for precise scaling of conventional spacers as well as new patterning applications put very stringent requirements on spacer thin film depositions and on control of spacer film properties during subsequent integration processes. The need for greatly improved spacer process step coverage, tighter thickness control, pattern effects and more stringent film properties requirements strongly influenced the transition from Chemical Vapor Deposition (CVD) to Atomic Layer Deposition (ALD) spacers in the industry.This paper discusses the properties of ALD silicon nitride and silicon oxide spacer films from the perspectives of ALD and MLD (Molecular Layer Deposition) techniques, precursor chemistries and compositional stability after subsequent integration steps like implant anneals and spacer sculpting reactive ion etching processes. Advanced imaging techniques like EELS (Electron Energy Loss Spectroscopy) and XPS (X-ray Photoelectron Spectroscopy) techniques have been used to analyze sidewall spacer transformation. Special attention has been paid to the microloading effect - the dependence of thin film deposition rate on pattern density [3]. Microloading data for CVD, MLD and ALD techniques are compared based on a specially designed microloading measurement vehicle. This is especially useful with geometries needing a sub nm tolerance and when patterning endpoint detection schemes are highly dependent on film properties.The effect of ALD deposition parameters on film electrical characteristics like dielectric breakdown and leakage are also delineated. Silicon strain engineering issues related to the implementation of ALD spacers and techniques aimed at varying and controlling an intrinsic stress level in ALD films are also discussed. The findings helped to optimize the existing ALD/MLD processes for conventional epi and source/drain spacers as well for oxide sidewall ALD spacers for SIT fins patterning and CD shrink on 14nm FinFET technology.

FinFET Devices and Integration

FinFET Devices and Integration

Advanced plasma etch technologies for nanopatterning

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45 nm through 14/10 nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques, such as litho-etch-litho-etch, sidewall image transfer, line/cut mask, and self-aligned structures, have been implemented to solution required device scaling. Advances in dry plasma etch process control across wafer uniformity and etch selectivity to both masking materials have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes, such as trilayer etches, aggressive critical dimension shrink techniques, and the extension of resist trim processes, have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across-design variation, defectivity, profile stability within wafer, within lot, and across tools has been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated total patterning solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. We will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

A new design of tunneling field-effect transistor (TFET) focusing on the compatibility to the current Si complementary-metal–oxide–semiconductor (CMOS) technology is proposed. In addition to use of the structural components of the state-of-the-art CMOS technologies, such as Σ-shaped embedded SiGe and the replacement gate techniques, two-step sidewall image transfer gate-patterning and channel recess process are adopted to form highly-scaled nanoscale TFET. Process integration scheme and the expected device characteristics are examined on the basis of technology computer-aided design (TCAD) simulation on 14-nm-gate model devices. Tunability of transfer characteristics with doping around tip region, control of short-channel effect with channel recess, and improvement of current drivaility with SiGe composition are studied. Design of the source region is found to be critical in controlling the current drivability of the device and output characteristics.