Sidewall Diffusion Research Articles

A Novel Method For Molybdenum Etching Using a Combination of Surface Oxidation By Ozone-Gas-Bake and Wet Selective Removal for Future Semiconductor Devices

As semiconductor devices continue to scale, it is important to evaluate new metals for narrower trench or via structures. Mo is a candidate because of its lower resistivity compared to the conventional metals, Cu or W. Mo is etched with wet chemistry using an oxidizer but increase in surface roughness is a problem. The model for increase in roughness is water insoluble MoO2 partially remains whereas MoO3 dissolves in the water via simultaneous "oxidation-dissolution" reactions. We have developed a novel cyclic process with O3 gas bake followed by oxidizer free wet process to separate the oxidation and dissolution and verified that surface roughness does not increase. The new process was tested with patterned wafer to look at residue on sidewall, pattern loading and oxygen diffusion. This method is showing promising results and is expected to be applied for use in manufacturing of future semiconductor devices.

Size effects on IMC growth of Cu/Ni/Sn-3.5Ag microbump joints during isothermal aging and prediction of shear strength using ANN

Significant downsizing trend is currently directing the advanced microelectronic packaging industry, which poses new challenges to the manufacturing process and reliability of high-density chip interconnections. In this paper, to investigate the size effect of microbump joints on the interfacial structure and bonding strength, the chip-to-chip bonding joints fabricated by microbumps of same Cu/Ni/Sn-3.5Ag construction but of various sizes were experimentally examined. After thermocompression bonding process to fabricate the chip-to-chip microbump interconnections, the intermetallic compound (IMC) growth on the Ni/Sn-3.5Ag interface during 150 °C isothermal aging was compared for joints of 100, 40 and 25 μm in diameter as well as 35, 25 and 15 μm in solder layer height, using field emission electron microscopy and electron probe microanalysis. A clear size effect on the thickness and morphology of Ni3Sn4 IMC was observed, showing thicker IMC in joints of smaller diameter and lower height. The Ni concentration distribution in the solder layer was verified to be dependent on the joint size, with possible reasons being enhanced sidewall diffusion and grain boundary diffusion through IMC grains in small-diametered joints, as well as shorter diffusion path in lower joints. The shear strength of chip-to-chip bonding vehicles was also found to be size-dependent. In addition, artificial neural network (ANN) approach was applied to establish the numerical correlation of structural factors and bonding strength. It was found that a properly constructed ANN model can successfully predict the influence of the complex combinations of geometric and interfacial factors with highly accurate output, providing an effective tool for design and optimization of microbump interconnection structures and processes.

Effect of Radius on Crystal Structure Selection in III–V Nanowire Growth

The radius of III-V nanowires is known to have an effect on the resulting crystal structure during particle-assisted growth; however, the causes behind this effect remain under debate. In this work, we use stochastic simulations of nanowire growth to evaluate how the radius (R) affects the growth dynamics and how this in turn affects the crystal structure selection. This is due to the geometry of the growing nanowire: The number of atoms in the seed particle scales with R3, and the number of III-V pairs per layer scales with R2. The influx of growth species to the seed can, for instance, scale with the surface area of the seed particle for direct impingement (?R2) or the perimeter of the nanowire for sidewall diffusion (?R1) or be radius-independent for substrate diffusion in some cases (?R0). These differences in radius dependencies cause the particle composition to change more rapidly for thinner nanowires, which in turn leads to nucleation at higher supersaturations and promotion of the wurtzite structure. In addition, the geometry can also make the influx V/III ratio dependent on the nanowire radius, which can influence the selection of crystal structure in different ways depending on the materials system and growth regime. (Less)

Quantitative investigation of the lateral diffusion of hydrogen in p-type GaN layers having NPN structures

This work quantitatively examined lateral diffusion of hydrogen in the (0001) in-plane direction in a Mg-doped p-type GaN layer sandwiched between n-type layers, based on the preparation and annealing of circular mesa structures having different radius values. Capacitance–voltage analyses and secondary ion mass spectrometry confirmed a decrease in the effective acceptor concentration along with an increase in the residual hydrogen concentration with increasing radius values, indicating hydrogen desorption through the sidewall and lateral diffusion. Considering the surface barrier to desorption, we estimated a lateral diffusion coefficient of 7 × 10−8 cm2 s−1 at 1123 K, reasonably reproducing the effect of the mesa radius.

High thermal stability ohmic contacts to nitride semiconductors with refractory metal sidewall diffusion barrier deposited by magnetron sputtering

GaN HEMTs are generally promising candidates for RF and switching power transistors due to their high breakdown strength and the high current density giving a low on-resistance. Low-resistance ohmic contacts are needed to reduce losses and self-heating. Conventional ohmic contacts use Ti and Al with a cap to avoid oxidation of the Al layer. Alternative ohmic metals for use with nitride semiconductors are being sought using Hf or Ta, which can be annealed at lower temperatures. That have been shown, the Au-free low temperature Ta/Al ohmic contacts fabricated with the refractory sidewall diffusion barrier have the lower contact resistance and the better surface morphology after the high temperature annealing. Normally-off p-gate high voltage GaN transistor based on Ta/Al ohmic contacts with the sidewall diffusion barrier have the higher drain-source current, lower gate-source current and higher source-drain breakdown voltage.

Uncertainty quantification in nanowire growth modeling – A precursor to quality semiconductor nanomanufacturing

Mitigating the uncertainties associated with nanowire growth models have significant ramifications for the quality and reliability of nanomanufacturing of semiconductor nanowires. This research is focused on the development of a sectional-based mechanistic model of nanowire growth and the determination of the level of impacts the model parameters have on the growth of nanowires, characterized in terms of their weight, diameter and length. After testing the model with experimental growth data of silica (Si) nanowire weight, ZnO average diameter and length, it was observed that the direct top impingement growth coefficient (αim) had the largest influence on the nanowire growth, in comparison to other model parameters→sidewall diffusion growth coefficient (αsw), maximum allowable growth weight or length (W(max)) and initial weight or length (W0). The knowledge of the impact of uncertainty in these parameters on the overall growth of the nanowire can be leveraged on for robust design of the nanofabrication process that will impact on the quality, reliability, yield and cost of nanomanufacturing.

Insights into gold-catalyzed plasma-assisted CVD growth of silicon nanowires

Understanding and controlling effectively the behavior of metal catalyst droplets during the Vapor-Liquid-Solid growth of nanowires are crucial for their applications. In this work, silicon nanowires are produced by plasma-assisted Chemical Vapor Deposition using gold as a catalyst. The influence of hydrogen plasma on nanowire growth is investigated experimentally and theoretically. Interestingly, in contrast to conventional chemical vapor deposition, the growth rate of silicon nanowires shows a decrease as a function of their diameters, which is consistent with the incorporation of silicon via sidewall diffusion. We show that Ostwald ripening of catalyst droplets during nanowire growth is inhibited in the presence of a hydrogen plasma. However, when the plasma is off, the diffusion of Au atoms on the nanowire sidewall can take place. Based on this observation, we have developed a convenient method to grow silicon nanotrees.

Formation of copper-based interconnects for GaAs monolithic microwave integrated circuits

Technological solutions are presented for forming interconnect metallization of GaAs monolithic microwave integrated circuits (MMICs) based on the W/Cu/WN x thin-film composition. A peculiarity of these solutions is that, for the first time, copper conductors with the surface completely surrounded by layers of diffusion barriers are created using the liftoff method traditionally employed for producing GaAs MMICs. Copper conductors 380 nm thick were deposited by E-beam evaporation, while the layers of planar and sidewall diffusion barriers based on W and WN x were sputtered. For successful formation of the sidewall diffusion barriers on the vertical surfaces of the copper conductors, the profile optimization of the photoresist mask was carried out. Modes of removing the photoresist mask are presented that enable effective elimination of the metallic “veils” formed on the vertical walls of the photoresist mask in the process of sputtering of diffusion barriers. The interconnects W/Cu/WN x were integrated into the manufacturing process of GaAs microwave low-noise amplifiers based on the pHEMT with 250 nm T-gates.

Influence of p-GaN shape on the light emission characteristics of InGaN nanodisk embedded p-i-n GaN nanorods

InGaN nanodisk embedded GaN nanorods (NRs) with different p-GaN morphologies were grown on Si(111) substrate by plasma-assisted molecular beam epitaxy. Tapered and non-tapered p-GaN top was obtained by varying the growth conditions namely growth temperature and N2 plasma power, and the morphology evolution was explained based on the interrelation between sidewall diffusion and direct impingement during the NRs growth. Photoluminescence measurements revealed higher light emission for tapered p-GaN when compared to non-tapered structure. APSYS simulations were further conducted to theoretically confirm the observed experimental results. Our results indicate that the fabrication of InGaN-GaN multi-quantum well NRs light emitting diodes (LEDs) with tapered top p-GaN will be a promising approach for the realization of high brightness LEDs.

Influence of gridded gate structure on gas sensing behavior of hydrogen

A gridded Pt/SiO2/Si MOS sensor for hydrogen detection has been fabricated on p-type ⟨100⟩ Si wafer having resistivity (1–6 Ω cm). The SiO2 and Platinum (Pt) gate thickness were kept about 10 nm and 35 nm. The performance of Pt gate MOS sensor was evaluated through C-V characteristics (capacitance vs voltage) upon exposure to H2 (250 ppm–4000ppm) at different frequencies (25 kHz and 50 kHz) in a closed chamber at air ambient atmosphere. The capacitance of the sensor decreases with increase in frequency as well as H2 gas concentration. The flat band voltage characteristics have been evaluated at different frequencies and concentrations. It decreases as the frequency and concentration of gas both increases. The maximum flat band voltage change was observed −0.6 V at 25 kHz. The sensor exhibits better sensitivity (∼88%) at low frequency (25 kHz). The high response of sensor is attributed to the side wall diffusion, increase in surface area caused by inner side wall and increase in porosity, increase in fixed surface state density, spill-over mechanism and change in interface state density on exposure of gas along with the formation of dipole layer.

Fabrication and characterization of gridded Pt/SiO2/Si MOS structure for hydrogen and hydrogen sulphide sensing

A gridded gate Pt/SiO2/Si MOS capacitor has been fabricated for detection of Hydrogen (H2) and Hydrogen Sulphide (H2S) gases. The MOS device was fabricated on P-type Si <100> (1–6 Ω cm) wafer with thermal oxide layer of thickness about 100 Å, whereas, Platinum (Pt) gate of ∼350 Å was deposited by thermal evaporation technique. The C–V (capacitance vs voltage) and G–V (conductance vs voltage) measurements have been performed for the evaluation of gas sensing behavior of fabricated MOS capacitor structure in H2 (250–4000 ppm) and H2S (1000–6000 ppm) gases at both room and 120 °C temperatures, in a closed chamber in air atmosphere. It has been observed that the value of capacitance decreases with increase in gas concentration. The fabricated MOS capacitor sensor has shown better sensitivity towards H2 (88.6%) at room temperature (∼25 °C) as compared to (∼45%) at 120 °C. Scanning electron microscopy (SEM) and Atomic force microscopy (AFM) studies have revealed the porous nature of the deposited metal film. The side wall diffusion, spillover of Hydrogen into oxide layer, increase in fixed oxide charge density, increase in surface area caused by gridded structure, the formation of dipole layer and change in interface state density on gas exposure, may be the mechanisms of gas sensing for improved sensitivity of the fabricated MOS device.

Role of sidewall diffusion in GaAs nanowire growth: A first-principles study

The molecular processes during the growth of GaAs nanowires in molecular beam epitaxy (MBE) are studied from first principles. For the wurtzite crystal structure of GaAs, which is formed exclusively in nanowire growth, potential energy surfaces for sidewall diffusion of Ga, As, and GaAs surface species are calculated using density functional theory. We compare materials transport on type-I and -II nanowires (with ${10\overline{1}0}$ and ${11\overline{2}0}$ facets of wurtzite GaAs, respectively) and discuss its role for materials supply to the growth zone at the nanowire tip. On the sidewalls of type-II nanowires, the diffusion barrier for Ga along the growth direction is particularly low, only 0.30 eV compared to 0.60 eV on type-I nanowires. For As adatoms, the corresponding diffusion barriers are 0.64 eV and 1.20 eV, respectively, and hence higher than for Ga adatoms. The GaAs molecule formed by the chemical surface reaction of Ga and As finds very stable binding sites on type-II sidewalls where it inserts itself into a chemical bond between surface atoms, triggering radial growth. In contrast, on type-I nanowires the GaAs molecule adsorbed with the As end towards the surface has a low diffusion barrier of 0.50 eV. Together with our previous finding that the gold particle at the nanowire tip is efficient in promoting dissociative adsorption of As${}_{2}$ molecules, we conclude that the influx of Ga adatoms from sidewall diffusion is very important to maintain stoichiometric growth of GaAs nanowires, in particular when a large V-III ratio is used in MBE.

Texture characterization of Cu interconnects with different Ta-based sidewall diffusion barriers

X-ray diffraction is used to assess the texture of narrow lines and study the impact of different sidewall diffusion barrier materials. All the Ta-based barriers developed a strong 〈1 1 1〉 texture in the scaled geometry, with little effect from sidewall growth. Comparisons were made with blanket wafers, demonstrating the pined grain structure in the narrow lines and contrasting change in texture due to re-crystallization in the unconstrained film. Furthermore, patterned lines showed significant anti-symmetric plane distribution influenced by high strains and twinning along the lines.

Role of nonlinear effects in nanowire growth and crystal phase

We study theoretically and experimentally nonlinear effects during the ``vapor-liquid-solid'' growth of semiconductor nanowires. Nonlinear growth equation considered contains kinetic coefficients from the surface and sidewall diffusion which can be of either signs. We predict four possible growth scenarios: (I) infinite growth; (II) decomposition; (III) averaging growth to a finite length; and (IV) continuing growth such that nanowires of small initial length decay and longer nanowires grow infinitely. We present the experimental evidence of nontrivial scenarios (II) and (IV) during the Au-assisted molecular-beam epitaxy of GaAs nanowires. Scenario (II) corresponds to the evaporation of GaAs nanowires during the annealing. Scenario (IV) is observed during two-step growth procedure where a low-temperature growth is followed by deposition at $630\text{ }\ifmmode^\circ\else\textdegree\fi{}\text{C}$. We show that the growth via scenario (IV) enables to control the crystal phase and to obtain the stacking-fault-free sections of zinc-blende GaAs NWs having only 15--20 nm in radius.

Gibbs-Thomson and diffusion-induced contributions to the growth rate of Si, InP, and GaAs nanowires

We present a general model for the vapor-liquid-solid nanowire (NW) growth rates which accounts for adatom diffusion from the substrate and sidewalls into the Au catalyst drop as well as the Gibbs-Thomson effect of elevated chemical potential in the drop with a curved surface. The growth model is compared with the experimental length-diameter dependences for InP and Si NWs grown via metal organic chemical vapor deposition (MOCVD) and GaAs nanowires grown via molecular beam epitaxy (MBE). We show that MBE growth is affected mainly by adatom diffusion from the substrate, whereas MOCVD growth is affected mainly by direct Au drop impingement and sidewall diffusion. The Gibbs-Thomson effect is shown to limit growth for smaller diameter nanowires. Fits for diffusion lengths and the Gibbs-Thomson radii are determined which explain the experimental length-diameter dependence observed.

Thirteen findings in ten minutes.

Nine architecture students in an architectural acoustics course studied the influence of design on the acoustic response of spaces. Thirteen of their projects will be presented, rapidly, with time to delve into some of them more deeply in response to questions from attendees. Areas of focus include: room shaping and balcony composition; ceiling and canopy height; canopy design; perception and preference of double sloped decays; side wall angle and orientation; room length; very tall ceilings; room width; side wall diffusion; mapping background noise levels; and frequency content of noise.

A comparison of various dielectric/metal sidewall diffusion barriers for Cu/porous ultra-low-K interconnect technology in terms of leakage current and breakdown voltage

A very thin dielectric flash layer (DFL) was used in addition to Ta for Cu/ultra-low- K (porous SiLK™) back-end technology. Atomic force microscopy showed that SiC DFL is superior to Si 3N 4 or SiO 2 DFL in terms of smaller surface roughness. It appears to the authors that the key point to get a very smooth DFL is to avoid the use of nitrogen-containing gases like NH 3, N 2 or N 2O during the DFL deposition process. An alternative explanation is that trimethylsilane is the better Si source compared to silane. Electrical testing showed that SiC DFL is superior to Si 3N 4 or SiO 2 DFL in terms of higher breakdown voltage.

Reduced surface sidewall recombination and diffusion in quantum-dot lasers

We examine the surface recombination rate in quantum-dot semiconductor lasers and determine the diffusion length (1.0 mum) and, for the first time, provide a value for surface recombination velocity (5times104 cm/s) in quantum-dot material. As a result of strong carrier confinement in the dots, these values are much lower than in comparable quantum-well lasers (5times105 cm/s and 5 mum, respectively) allowing the creation of narrow (2-3 mum wide) lasers with comparable threshold currents to those of broad area devices

Influence of the sidewall diffusion barrier on the transport properties of advanced Cu/low- k interconnects

We present the impact of the sidewall diffusion barrier on the dielectric properties of advanced Cu/porous ULK interconnects. From the temperature dependence of the leakage currents, the conduction mechanisms can be compared. The high field transport is consistent with a Poole–Frenkel model, and the low field with a variable range hopping model, from which a defect density near Fermi level is obtained. The complex surface of the etched porous ULK is better suited to a conformal and continuous barrier, such as CVD TiN, which highlight the challenge to get very thin but defect-free metal barrier for future generations.

Investigation of dielectric/metal bilayer sidewall diffusion barrier for Cu/porous ultra-low-k interconnects

A dielectric/metal bilayer structure of a-SiC:H/Ta was integrated and investigated for application as a sidewall diffusion barrier in a Cu/porous ultra-low-k interconnect structure. Different dielectric/metal bilayer thicknesses were investigated. The electrical tests and physical analyses indicate that this a-SiC:H/Ta bilayer structure is a more efficient sidewall diffusion barrier than the conventional physical vapor deposited (PVD) multistack TaN/Ta metal barrier. With a similar total sidewall barrier thickness, an even better barrier integrity and reliability can be achieved by using a thicker a-SiC:H layer and a correspondingly thinner Ta barrier. This achievement is mostly attributed to the surface modification and sealing of the porous ultra-low-k surface by the a-SiC:H layer. Thus, the scenario of the barrier failure due to defects in the Ta (or TaN) barrier layer directly deposited on rough porous ultra-low-k material is avoided. Bias-temperature stress (BTS) and time-to-failure (TTF) studies indicate the Copper penetration through the sidewall barrier into the porous dielectric was the dominating failure mechanism in the conventional PVD TaN/Ta barrier and bilayer barrier of thinner a-SiC:H (14 /spl Aring/) and thicker Ta (71 /spl Aring/) layers, although the latter enhanced the lifetime of interconnect structures considerably. The bilayer barrier consisting of a thicker a-SiC:H (60 /spl Aring/) and correspondingly thinner Ta (53 /spl Aring/) layers was more robust to protect the sidewall region so that this sidewall Cu diffusion induced failure mechanism was no longer found in Cu/porous ultra-low-k interconnect structures even after thermal stress at 200/spl deg/C for 120 h.