Side Gate Research Articles

Unprotected edge modes in quantum spin Hall insulator candidate materials

The experiments in quantum spin Hall insulator candidate materials, such as HgTe/CdTe and InAs/GaSb heterostructures, indicate that in addition to the topologically protected helical edge modes, these multilayer heterostructures may also support additional edge states, which can contribute to scattering and transport. We use first-principles calculations to derive an effective tight-binding model for HgTe/CdTe, HgS/CdTe, and InAs/GaSb heterostructures, and we show that all these materials support additional edge states which are sensitive to edge termination. We trace the microscopic origin of these states back to a minimal model supporting flat bands with a nontrivial quantum geometry that gives rise to polarization charges at the edges. We show that the polarization charges transform into additional edge states when the flat bands are coupled to each other and to the other states to form the Hamiltonian describing the full heterostructure. Interestingly, in HgTe/CdTe quantum wells the additional edge states are far away from the Fermi level so that they do not contribute to the transport, but in the HgS/CdTe and InAs/GaSb heterostructures they appear within the bulk energy gap, giving rise to the possibility of multimode edge transport. Finally, we demonstrate that because these additional edge modes are nontopological it is possible to remove them from the bulk energy gap by modifying the edge potential, for example, with the help of a side gate or chemical doping.

Experimental investigation of turbulent flow in a rectangular bonneted slide gate and eliminating random fluctuating loads

Bonneted slide gates are widely used in dam bottom outlets for flow regulation. High kinetic energy flow generates turbulence, which induces vibrations in bonneted slide gates under partially open conditions. Significant vibrations can indicate problems and cause damage or expedited deterioration of the gate if left unchecked. This experimental study focuses on two aspects: turbulent flow formation due to rectangular bonneted slide gates and elimination of random fluctuating loads on the gate using a turbulence inhibitor. Five reservoir heads were combined with nine gate openings (10%–90%) to produce 45 different discharges of 12–182 l/s. The different types of the gate flow create different turbulence and random loads based on the water–air mixture and the kinetic energy of the flow. Flow analysis indicates considerable random static pressure fluctuations under the slide gate. The results show the formation of swirling secondary flows in the gate's side guide slots, and their movement and collision with the gate are the leading cause of the turbulent multiphase flow and random fluctuations in static pressure. Also, the use of turbulence inhibitors on the gate can prevent the formation of secondary flows, which results in a 98.92% reduction in the amplitude of random static pressure fluctuations and the elimination of the random fluctuating loads on the slide gate. After removing the swirling secondary flows, a stable air boundary layer was formed under the gate. Finally, the gate flow changed from a turbulent two-phase flow to a steady single-phase jet of water.

Novel Stacked Passivation Structure for AlGaN/GaN HEMTs on Silicon With High Johnson’s Figures of Merit

We present a high-performance AlGaN/GaN high electron mobility transistors (HEMTs) on silicon substrate with novel stacked passivation layer (HfO2/SiO2). The stacked passivation structure can effectively modulate the electric field and reduce the electric field peak on the gate side, thus improving the breakdown voltage of the device. The prepared device with a gate length of 450 nm has a unit current gain cutoff frequency (fT) of 31.5 GHz, a maximum oscillation frequency (fMAX) of 46.3 GHz, and a three-terminal OFF-state breakdown voltage (BVgd) of 140 V at the gate-drain distance of 2.3 μm. The estimated Johnsonfs figure of merit (J-FOM=BVgd×fT) is 4.4 THz∙V, which is three and five times higher than that of the device with single HfO2 passivation layer and single SiO2 passivation layer, respectively. Furthermore, a significant suppression of the current collapse ( 5.7%) is observed due to the electric field redistribution near the drain region. The results show that the AlGaN/GaN HEMTs with stacked passivation layer proved to be a promising candidate for high-performance radio frequency (RF) power device applications.

A Design of Wireless Power Receiver With Gate Charge Recycled Dual-Mode Active Rectifier and Step-Down Converter With 88.2% System Efficiency for Power Management IC

This article presents a power management integrated circuit for a wireless power receiver unit. A dual-mode high-efficiency active rectifier design is based on alliance for wireless power (A4WP) and wireless power consortium (WPC) standards. A gate charge recycling technique is proposed in the dual-mode active rectifier so that the current generated by the switching of the high side gate driver can be recycled to the rectifier output voltage in order to enhance efficiency. A step-down dc–dc converter with a proposed bootstrap circuit and dynamic pull-up resistor gate driver circuit is designed. The chip is implemented in a 0.18-μm bipolar-CMOS double-diffused metal-oxide-semiconductor process. The total die area, including the pad, is 2.64 mm × 2.6 mm. The measurement results show that the active rectifier achieves peak power conversion efficiency (PCE) of 94.7% and generates an output voltage of 7.68 V in WPC mode and 9.1 V with 93.4% efficiency in A4WPC mode. The input voltage varies from 10 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P-P</sub> –12 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P-P</sub> . Similarly, the step-down dc–dc converter obtains a peak PCE of 93.2% at a load current of 500 mA while producing an output voltage of 5 V. The overall system efficiency at A4WP and WPC mode are 86.7% and 88.2%, respectively.

Suppression of Kink in the Output Characteristics of AlInN/GaN High Electron Mobility Transistors by Post-Gate Metallization Annealing

In this paper, we report the effect of post-gate metallization annealing on the performance of GaN-based High Electron Mobility Transistors (HEMTs). The performances of HEMTs annealed at 200 °C (HEMT1) and at 400 °C (HEMT2) for 5 minutes in N2 ambient are compared. While there is a kink in the output characteristics of HEMT1, there is no such kink in the output characteristics of HEMT2. The kink is attributed to impact ionization in the GaN channel. Surface and interface traps of HEMT1 increase the peak electric field at the drain side gate edge and cause impact ionization. The post-gate metallization annealing at a higher temperature reduces the surface and interface traps, which reduces the peak electric field in HEMT2 and suppresses impact ionization. This is substantiated by TCAD simulations. Threshold voltage instability on the application of negative gate bias stress was also examined for these devices. A positive shift in threshold voltage was observed in HEMT1 on the application of negative gate bias stress, whereas the corresponding shift was negative in HEMT2, indicating the presence of two different types of traps in HEMT1 and HEMT2.

Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection

Semiconductor technologies have gained wide-spread attention across industries due to its use in varied digital signal processing units, healthcare-devices, industrial communication, science and technologies, entertainment, smart devices etc. However, high design-complexities, untrusted foundries, third-party processors etc., have raised the concern of intrusion, particularly Hardware Trojans. Hardware Trojan, a specifically designed micro-intruder that can cause data breaches, system malfunctions etc. And hence may result disastrous consequences. To alleviate such problems, though different methods have been suggested for Trojan detection; however, pre-manufacturing methods can't guarantee Trojan-free design due to non-trusted Foundries and Third-party IPs. Similarly, post-manufacturing methods like side channel analysis or gate -level netlist are limited due to highly complex design, large structure and unavailability of universal golden design structures. Considering it as motivation, this paper proposes a robust register transfer logic (RTL) analysis assisted multi-parameter-based machine learning-driven Hardware Trojan detection system. We applied delay, power consumption and resource utilization profiles to perform Trojan detection over AES-256 circuits. Aforesaid features were extracted using VIVADO tool, which were further employed for resampling process using SMOTE, SMOTE-ENN, SMOTE-Borderline algorithms. Here, the use of resampling intended to alleviate data-imbalance or skewness. Moreover, it helped retaining sufficiently large features for machine learning based training. The resampled features were processed for feature selection using Significant Predictor Test, Cross-Correlation Test and Principal Component Analysis (PCA), distinctly. The selected features were trained using a novel heterogenous ensemble learning model encompassing a total of 11 base-classifiers belonging to Naïve Bayes, Neuro-computing, Decision Tree, Random Forest, Extra Tree classifier and Bagging-AdaBoost algorithms. Applying the maximum voting ensemble, the proposed model performed path-level Trojan detection, where the simulated results affirmed accuracy, F-Measure and Area Under Curve (AUC) of almost 100%, which is higher than any known approaches towards Hardware Trojan detection.

Suppression of Impact Ionization by Carbon Doping in the GaN Buffer Layer in InAlN/GaN‐Based High Electron Mobility Transistors

Herein, the impact ionization in InAlN/GaN‐based high electron mobility transistors (HEMTs) is studied for the first time. It is shown that the carbon doping in the GaN buffer layer can suppress impact ionization by reducing the electric field at the drain side gate edge. For comparison, two wafers are taken. In one wafer (D1), the GaN buffer layer is unintentionally doped, and in another wafer (D2), the buffer layer is carbon doped with a doping concentration of at a distance of 500 nm from the InAlN–GaN interface. The impact ionization is probed from the bell‐shaped nature of theIG – VGScharacteristics. The bell‐shaped nature is observed in D1 for the drain‐to‐source voltage (VDS) 6 V, whereas it is absent in D2. Floating source measurements confirm the occurrence of impact ionization in D1. At a lower temperature (−60 °C), the impact ionization rate of D1 increases even though there is no sign of impact ionization in D2. A technology computer‐aided design simulation shows that the peak electric field at the drain side gate edge of D2 is lower than that of D1.

A Hybrid Dynamic Voltage Sharing Scheme for Series-connected SiC MOSFETs with Single Gate Drive

At present, the voltage level of a commercial SiC MOSFET can hardly meet the requirements of high-voltage field. For the sake of achieving the application of MOSFETs in high-voltage fields, the method of series-connected MOSFETs has become a practical and effective solution. However, multiple series-connected SiC MOSFETs face the problem of voltage unbalance, especially dynamic voltage unbalance. Generally, the problem of dynamic unbalance could be solved using load side voltage sharing schemes or the methods of gate side. This paper uses a hybrid dynamic voltage sharing scheme for the single-driven series-connected SiC MOSFETs. That is to say, based on a sequential lagging single gate drive topology, combining active clamping circuits with RCD snubber circuits are introduced to solve the problem of dynamic voltage unbalancing of the whole module in this paper. Compared to the circuit without any dynamic voltage sharing scheme, the dynamic voltage imbalance degree of the circuit with a hybrid dynamic voltage sharing scheme is decreased to 3.75% during the switching-on and switching-off periods. The equalization effect would be verified through the simulation under clamped inductive load in LTspice.

Graphene-Based Quantum Hall Interferometer with Self-Aligned Side Gates.

The vanishing band gap of graphene has long presented challenges for making high-quality quantum point contacts (QPCs)─the partially transparent p-n interfaces introduced by conventional split gates tend to short circuit the QPCs. This complication has hindered the fabrication of graphene quantum Hall Fabry-Pérot interferometers, until recent advances have allowed split-gate QPCs to operate utilizing the highly resistive ν = 0 state. Here, we present a simple recipe to fabricate QPCs by etching a narrow trench in the graphene sheet to separate the conducting channel from self-aligned graphene side gates. We demonstrate operation of the individual QPCs in the quantum Hall regime and further utilize these QPCs to create and study a quantum Hall interferometer.

1.2 kV Stepped Oxide Trench Insulated Gate Bipolar Transistor with Low Loss for Fast Switching Application

In this article, a gate engineering technique is used in Insulated gate bipolar transistor (IGBT) for fast switching applications. The modification consists of stepped oxide pattern at gate terminal with n-poly layer sandwiched between two p-poly layers. The oxide thickness increases from top to bottom so as to create a stepped structure. The oxide thickness is lesser on channel side and higher on collector side. The less thickness beside the channel increases gate to emitter charges (QGE) by extracting extra charges along the channel. The presence of these extra charges also increases the collector current density resulting reduction in the area specific on-resistance (Ron.A). On the other hand, the higher thickness at the bottom side of gate offers reduction in gate to collector charges (QGC). Furthermore, to elongate the impact of QGC reduction, the low doped p-col region has been facilitated which also play an important role to increase the breakdown voltage by reducing corner electric field. This p-col region creates charge extraction path to swept out charges from the drift region while turn-off event and makes the device to turn-off quickly. The collective improvement in QGE and QGC provides fast switching to the proposed device by improving turn-off time by 63% and also reduces turn-off loss (Eoff) by 55% as compared to the conventional device. Furthermore, the change in the workfunction also provides the reduction of channel peak electric field and offers 10% increment in the BV as compared to the conventional IGBT.

독립문 편액 서자(書者) 연구

There are two theories about the lyricist of A framed picture written on the south and north sides of Independence Gate. It was written by Lee Wan-yong(1858-1926), who was patriotic but degenerated into a traitor, and by Dongnong Kim Ga-jin(1846-1922), who devoted himself to modernization of Joseon and campaigned for independence until he turned his back on the world. Independence Gate is a national monument modeled after the Arc de Triomphe in Paris in the form of a 14.2m high and 11.48m wide stone gate that greeted the envoys of Cheong since the Independence Association advocated the construction of Independence Gate in 1896. The south side of Independence Gate is engraved in Korean, and The north side is engraved with three letters of Independence Gate in Chinese characters. As both Lee Wan-yong and Kim Ga-jin were known as the best handwritings of the time, it is highly likely that they wrote the compilation of the Independence Gate. In addition, Lee Wan-yong was the chairman of the Independent Association and the foreign minister of the Joseon government at the time of the establishment of the Independent Gate, and Kim Ga-jin was also a member of the Independent Association and a high-ranking official of Joseon. Therefore, it is considered reasonable to interpret the answer to who wrote the compilation of the independent text in a calligraphy manner through the genuine enemies left by Lee Wan-yong and Kim Ga-jin. Therefore, this paper analyzes the calligraphy context of Lee Wan-yong and Kim Ga-jin and the font characteristics of similar handwriting left by them based on two different theories about independent writers.

Expression level of Sec62 modulates membrane insertion of marginally hydrophobic segments

In the endoplasmic reticulum (ER) membrane, transmembrane (TM) domain insertion occurs through the Sec61 channel with its auxiliary components, including Sec62. Sec62 interacts with the Sec61 channel and is located on the front side of the Sec61 lateral gate, an entry site for TM domains to the lipid bilayer. Overexpression of Sec62 led to a growth defect in yeast, and we investigated its effects on protein translocation and membrane insertion by pulse labeling of Sec62 client proteins. Our data show that the insertion efficiency of marginally hydrophobic TM segments is reduced upon Sec62 overexpression. This result suggests a potential regulatory role of Sec62 as a gatekeeper of the lateral gate, thereby modulating the insertion threshold of TM segments.

Unjamming strongly compressed rafts: Effects of the compression direction.

We experimentally study the unjamming dynamics of strongly compressed particle rafts confined between two fixed walls and two movable barriers. The back barrier is made of an elastic band, whose deflection indicates the local stress. The front barrier is pierced by a gate, whose opening triggers local unjamming. Prior to gate opening, the rafts are quasistatically compressed by moving only one of the two barriers, in the vicinity of which folds form. Using high-speed imaging, we follow the raft relaxation with folded, jammed, and unjammed areas and measure the velocity fields inside and outside the confined domain. Two very different behaviors develop. For rafts compressed by the back barrier, only partial unjamming occurs. At the end of the process, many folds remain and the back stress does not relax. The flow develops mostly along the compression axis and the particles passing the gate form a dense raft whose width is the gate width. For rafts compressed at the front, quasitotal unjamming is observed. Almost no folds persist and only minimal stress remains, if any. The particles flow along the compression axis but also normally to it and form a rather circular and not dense assembly. Both the force chain network orientation and the initial fold location could cause the unjamming difference. Other effects, such as a different pressure field or simple steric hindrance, cannot be excluded.

Effect of Sec62 on the conformation of the Sec61 channel in yeast

Most eukaryotic secretory and membrane proteins are funneled by the Sec61 complex into the secretory pathway. Furthermore, some substrate peptides rely on two essential accessory proteins, Sec62 and Sec63, being present to assist with their translocation via the Sec61 channel in post-translational translocation. Cryo-electron microscopy (cryo-EM) recently succeeded in determining atomistic structures of unbound and signal sequence-engaged Sec complexes from Saccharomyces cerevisiae, involving the Sec61 channel and the proteins Sec62, Sec63, Sec71 and Sec72. In this study, we investigated the conformational effects of Sec62 on Sec61. Indeed, we observed in molecular dynamics simulations that the conformational dynamics of lateral gate, plug and pore region of Sec61 are altered by the presence/absence of Sec62. In molecular dynamics simulations that were started from the cryo-EM structures of Sec61 coordinated to Sec62 or of apo Sec61, we observed that the luminal side of the lateral gate gradually adopts a closed conformation similar to the apo state during unbound state simulations. In contrast, it adopts a wider conformation in the bound state. Furthermore, we demonstrate that the conformation of the active (substrate-bound) state of the Sec61 channel shifts toward an alternative conformation in the absence of the substrate. We suggest that the signal peptide holds/stabilizes the active state conformation of Sec61 during post-translational translocation. Thus, our study explains the effect of Sec62 on the conformation of the Sec61 channel and describes the conformational transitions of Sec61 channel.

Threshold voltage of p-type triple-gate junctionless transistors

The threshold voltage of rectangular p-type triple-gate junctionless transistors (JLTs) is studied experimentally using the transconductance derivative (dgm/dVg) method, after correcting the drain current from the impact of series resistance. The effect of series resistance on the dgm/dVg behavior is highlighted. In the investigated devices, the high series resistance affects the dgm/dVg behavior more than the short-channel effects. The results show that, in addition to the flat-band voltage, for the first time two threshold voltages Vth1 and Vth2 are observed within the partial depletion region in devices with channel length varying from 95 to 25 nm. Numerical simulations of the holes density distribution reveal the absence of corner effects due to the unique bulk neutral conduction, whereas Vth1 and Vth2 correspond to the threshold voltages of the side gates and top gate, respectively. The correct extraction of the flat-band voltage has been confirmed with numerical simulations of the holes density distribution. Experimental measurements of p-type JLTs with variable being the fin width indicate that the threshold voltages Vth1 and Vth2 are due to the different interface states density at the side and top gates.

Quasi-analytical model of surface potential and drain current for trigate negative capacitance FinFET: a superposition approach

Negative capacitance (NC) obtained from the ferroelectric polarization switching is a widely adopted approach for the realization of low power, high-performance devices. In this paper, for the first time, we have developed a 3D quasi-analytical model for the surface potential and drain current of the trigate NC-FinFET using the superposition approach. Till date, only double gate (DG) uniformly doped NC-FinFET structures have been explored, which does not reveal the practicality of the device. Therefore, we perform an extensive device evaluation: (a) by solving the Poisson’s equation separately for the side gates (DG) and the top gate to acquire a complete model for trigate FinFET using the superposition principle; (b) to mimic the actual source/drain (S/D) doping, we included Gaussian doping in our proposed model; (c) with the incorporation of the laterally extended gate and S/D underlap. The model data are found in good agreement with the well-calibrated simulation data. We have taken the parabolic approximation method and appropriate boundary conditions to solve the Poisson’s equation.

A Ballistic Transport Nanodevice Based on Graphene Nanoribbon FET by Enhanced Productivity for Both Low-Voltage and Radio-Frequency Scopes

The top performance in both the low-voltage and radio frequency (RF) scopes has been nominated for an unique nanodevice made from a graphene nanoribbon with an extremely short gate length (7.5 nm) in this study. Two distinct material engineering options were used, yielding some interesting outcomes. Due to the use of an ultrascale GNRFET in this study, the band structure non-linearity in the Dirac point and the energy-position dependent effective mass model for dual material gate architectures were examined for the first time. The NEGF formalism is used to carry out both the low-voltage and RF research using a three-dimensional (3D) Poisson equation. Low-voltage high performance has been validated by monitoring the key parameters in the terms of on current (Ion), off current (Ioff), Ion to Ioff ratio, subthreshold swing, and drain induced barrier lowering (DIBL) for the proposed device as compared to other structures under the study. The RF performance is examined by evaluation of essential parameters in the cases of parasitic gate capacitance, intrinsic cut-off frequency, intrinsic delay time, and transconductance. Indeed, a device with a higher source side gate work function than it does on the drain side is proposed will shift the energy band from the device’s half to the drain electrode, altering carrier outflow. In addition, the performance of non-linearity and RF intermodulation distortion has been analyzed for all devices under investigation in order to attain the best attitude toward the suggested device in comparison to the other devices under investigation in this work.

Plastic filling simulation comparison analysis of the gating system in injection moulding parameter

The paper is discussed the anticipation of the simulation software precision with the real moulding process by setting up the distinctive metering stroke separation. The Inventor CAD software was used to design the product experiment and perform the simulation by applying MoldFlow application to produce the processing parameter defining for the injection moulding machines. The results predicted by this filling simulation appears reasonable result as compared to the injected product. Prediction analysis given by the software is exceptionally valuable for the injection moulding parameter setting machines which can diminish the time of mould setup and can reduce the trial stage on the production line. The gating system is the most crucial part in injection moulding process and the limitation is to get the accurate filling time and injection pressure to ensure the cavity is fully filled before the material at the gate solidify. Gating system configurations are utilized to optimize the filling conditions of injection moulding parts. This important element was developed for achieving product quality. The utilize of simulation software is exceptionally supportive in the model designing stage to predict the quality and process capacity for the product. This paper presents the filling simulation of the side gate system to the injection moulding parameter.

Highly sensitive and selective H2S sensors with ultra-low power consumption based on flexible printed carbon-nanotube-thin-film-transistors

Flexible printed carbon-nanotube-thin-film-transistors (CNT-TFTs) with characteristics of low cost, low operating voltage, low power consumption, and signal amplification have great potential for emerging electronics powered by self-powered systems or low-power density thin-film solar cells. In this work, we have fabricated flexible printed CNT-TFTs using the printing process to selectively deposit semiconducting CNTs in device channels as channel materials, printed silver electrodes as side gates, and printed ion gel as the dielectric layer. The as-prepared TFTs exhibited an extremely high sensitivity to H2S (up to 1565% ppm-1) at room temperature (25 ℃) and the relative humidity (RH) of 5%, excellent signal amplification (response increased from 1% to 4045.5% towards 2 ppm H2S), ultra-low working power consumption (1.03 nW under 2 ppm H2S), excellent selectivity, fast response/recovery time (10 s/26 s) and great mechanical flexibility (stable after 10,000 times bending with 5 mm radius). The outstanding improvement of sensor characteristics was related to the enrichment and absorption of H2S by ionic liquids, and the resistor-mode device's response to 2 ppm H2S increased from ~1% to 80% after the device channel was covered by ion gel. To the best of our knowledge, our H2S sensors demonstrated the recorded low power consumption (1.03 nW) and high response (4045.4%) when exposed to 2 ppm H2S at room temperature, making our sensors a promising candidate for portable applications in gas detection.

Rapid, Multianalyte Detection of Opioid Metabolites in Wastewater.

By monitoring opioid metabolites, wastewater-based epidemiology (WBE) could be an excellent tool for real-time information on the consumption of illicit drugs. A key limitation of WBE is the reliance on costly laboratory-based techniques that require substantial infrastructure and trained personnel, resulting in long turnaround times. Here, we present an aptamer-based graphene field effect transistor (AptG-FET) platform for simultaneous detection of three different opioid metabolites. This platform provides a reliable, rapid, and inexpensive method for quantitative analysis of opioid metabolites in wastewater. The platform delivers a limit of detection 2-3 orders of magnitude lower than previous reports, but in line with the concentration range (pg/mL to ng/mL) of these opioid metabolites present in real samples. To enable multianalyte detection, we developed a facile, reproducible, and high-yield fabrication process producing 20 G-FETs with integrated side gate platinum (Pt) electrodes on a single chip. Our devices achieved the selective multianalyte detection of three different metabolites: noroxycodone (NX), 2-ethylidene-1,5-dimethyl-3,3-diphenylpyrrolidine (EDDP), and norfentanyl (NF) in wastewater diluted 20× in buffer.