SiC MOSFET Research Articles

Temperature-Dependent Evaluation of Commercial 1.2 kV, 40 mΩ 4H-SiC MOSFETs: A Comparative Study between Planar, One-Side Shielded Trench, and Double Trench Gate Structures

This research investigates the static and dynamic characteristics of 4H-Silicon Carbide (SiC) MOSFETs with different gate structures: planar (Device A), one-side shielded trench (Device B), and double trench (Device C). We analyze threshold voltage, on-state resistance, transconductance, gate-to-source capacitances, and reverse transfer/miller capacitances with gate bias. Additionally, non-linear charges, including input charge, miller plateau, and total gate charge, are examined. Switching losses are assessed over a temperature range of 25° C to 125° C. Our findings reveal distinct performance differences, offering valuable insights for optimizing SiC MOSFETs in electric vehicle applications.

Comparison of the Surge Current Capabilities of SBD-Embedded and Conventional SiC MOSFETs

We demonstrated that the surge current capability of 3.3 kV Schottky-barrier-diode-embedded (SBD-embedded) SiC MOSFETs is equivalent to that of conventional SiC MOSFETs and three times higher than that of SiC SBDs. Furthermore, we revealed that the bipolar degradation attributed to the repetitive surge stress of high current density was negligible, which can be explained by the small total area of the expanded stacking faults (SFs) caused by the limited total period of conduction of the body diodes.

3<sup>rd</sup> Quadrant Surge Current SOA of SiC MOSFETs with Different Voltage Class

The aim of this work is to investigate the 3rd quadrant safe operating area (SOA) of different voltage class SiC MOSFETs under surge current conditions depending on the gate-source voltage. The extent to which an applied gate-source voltage can influence the surge current capability was investigated. For 650 V and 1.2 kV voltage class devices, surge current capability was higher with channel-on mode. However, this behavior was vice-versa for 2 kV and 3.3 kV devices. In this investigation, during the surge current event, the gate-source voltage was switched between different values to optimize the resulting voltage drop. This method can reduce power dissipation during a surge current event, especially for high voltage class SiC MOSFETs.

1.2 kV SiC MOSFET with Low Specific ON-Resistance and High Immunity to Parasitic Turn-On

With the capability to switch at high speed, there are important concerns about Parasitic Turn-On (PTO) when using SiC MOSFETs in switching applications with fundamental half-bridge configuration [1]. In this work, we present 1200V SiC planar MOSFETs with low specific ON-resistance (Rsp), fast switching characteristics and high immunity to PTO. The PTO immunity is verified by experimental comparison to several commercially available SiC MOSFETs.

Analysis of Electrothermal Imbalance of Hard-Switched Parallel SiC MOSFETs through Infrared Thermography

This paper provides an experimental investigation through infrared thermography of the steady-state temperature imbalance arising in parallel SiC MOSFETs. A switched-mode boost power converter based on two arrays of 4 parallel 1.2 kV MOSFETs is selected as a case-study. The analysis aims at proving that a proper device arrangement can minimize the thermal imbalance in the absence of circuit layout optimization.

Frequency Investigation of SiC MOSFETs C-V Curves with Biased Drain

SiC MOSFETs still suffers from some open issues, such as the high density of defects existing at the SiC/ SiO2 interface. In order to characterize such interface, a non-destructive investigation technique should be employed. In this work, we investigate the measurement of Gate capacitance with biased Drain. More in detail, the effect of frequency on such curves is considered. The analysis is performed using both in experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region which reduces its height as frequency increases.

Junction-Controlled-Diode-Embedded SiC-MOSFET for Improving Third Quadrant and Turn-On Characteristics

In this paper, we propose a novel 1200V SiC MOSFET featuring the embedded junction-controlled-diode (JCD-MOSFET) and demonstrate its static and dynamic characteristics through TCAD simulations. Without sacrificing blocking and conduction performance, the adoption of JCD can effectively reduce knee voltage to 1.7V based on unipolar carrier conduction mode. Due to the reduced peak reverse recovery current and reverse recovery charge, the JCD-MOSFET achieves 30.8% lower turn-on losses than conventional MOSFET. Meanwhile, the fabrication process for the JCD-MOSFET is the same as conventional MOSFET without an extra mask. This proposed JCD-MOSFET prototype shows great potential in target applications in the near future.

Investigation of BPD Faulting under Extreme Carrier Injection in Room vs High Temperature Implanted 3.3kV SiC MOSFETs

Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x1018 cm-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x1019 cm-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

SiC MOSFET Gate Oxide Quality Improvement Method in Furnace Thermal Oxidation with Lower Pressure Control

We have investigated carbon behavior resulting from pressure control in furnace thermal oxidation process and evaluated the effect on gate oxide quality resulting from this pressure control. In order to investigate the potential reduction of carbon defects by reducing CO and CO2, an analysis of oxidized SiC wafers was conducted. To evaluate the effect of pressure control related carbon component change during thermal oxidation, QBD characteristic was evaluated in SiC MOS Capacitance. The analysis results revealed on observable decrease in carbon at the SiO2/SiC interface and the SiO2 layer. The QBD results shown that improved at lower pressure better than those obtained in the general pressure.

Body Diode Reliability of 4H-SiC MOSFETs as a Function of Epitaxial Process Parameter

In this paper, the authors continue the experimental evaluation of bipolar degradation for different 1.2 kV SiC MOSFETs. All the devices are stressed by pulsed repetitive forward current through the body diode with current densities varying from 1000 A/cm2 up to 5000A/cm2. The 1.2 kV SiC MOSFETs are split into two major groups based on the differences in epitaxial material (Type A and Type B) that are subjected to the pulsed forward current stress through the body diode. Additionally, there is a third group with Type B epitaxial material, where p+ implantation process at different temperature is applied to evaluate potential impact on bipolar degradation. Devices are electrically characterized on the Keysight B1505A power device analyzer, both before and after stress testing to trace the drift in the electric parameters. Lastly, the drift in parameters observed in some of the devices, are additionally correlated by an electroluminescence (EL) and scanning acoustic tomography (SAT) analysis.

Comparison of Si and SiC MOSFETs responses to electrical stress and the observation of parameter recovery in SiC MOSFET by stress superposition

In this study we examined the effects of room temperature DC and AC electrical stress on Si and SiC n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). Measurement of threshold voltage, transconductance, subthreshold swing, charge pumping, and gate oxide breakdown are used to compare the impact of stress on Si MOSFETs and SiC MOSFETS, as well as to understand the processes of carrier injection and trapping at oxide and interface defects. DC stress is observed to promote negative charge buildup in the gate oxide and interface in Si MOSFETs. However, in SiC MOSFETs the net charge buildup sign alternates between negative and positive as the DC stress polarity is changed from positive to negative, respectively. For the same stress level, relative degradation in parameters of SiC MOSFETs are significantly smaller than those in Si MOSFETs, where in the latter interface state density, conductance, and subthreshold swing have degraded by up to 400%.The change of charge buildup sign explains our observation that degradation in SiC MOSFETs subjected to AC bipolar stress is insignificantly small, whereas AC stressing of Si MOSFETs is observed to be much more severe. Also, the superposition of alternating DC stress polarity eliminates the stress induced degradation in SiC MOSFETs thus enabling a straightforward process for parameter reconfiguration and recovery.

Design of on-board energy storage system using SiC MOSFET

Design of on-board energy storage system using SiC MOSFET

4H-SiC 64 pixels CMOS image sensors with 3T/4T-APS arrays

For radiation-hardened CMOS image sensors (CIS), 4H-SiC 64 pixel array CIS were developed, and real time imaging with an operation frequency of 30 Hz was demonstrated. Two types of pixel arrays with a 3-transistor active pixel sensor (3T-APS) and a 4-transistor active pixel sensor (4T-APS) were fabricated with SiC MOSFETs, UV photodiodes and 3-layered Al interconnections. The SiC pixel arrays were combined with peripheral circuits and an optical lens, and SiC 64 pixel CIS with 3T-/4T-APS arrays were developed.

Calculation and Analysis of the Dynamic Turn-On Process of SiC MOSFET Based on a Piecewise Linearization Method

Calculation and Analysis of the Dynamic Turn-On Process of SiC MOSFET Based on a Piecewise Linearization Method

Investigation on Gate Oxide Degradation of SiC MOSFET in Switching Operation

Investigation on Gate Oxide Degradation of SiC MOSFET in Switching Operation

Flexible Rogowski current probes in measurements of ultra-fast SiC MOSFET modules – limitations and challenges

Flexible Rogowski current probes in measurements of ultra-fast SiC MOSFET modules – limitations and challenges

Gate driver, snubber and circuit design considerations for fast‐switching series‐connected SiC MOSFETs

Gate driver, snubber and circuit design considerations for fast‐switching series‐connected SiC MOSFETs

Efficiency Optimization in Parallel LLC Resonant Inverters with Current-Controlled Variable-Inductor and Phase Shift for Induction Heating

This paper presents a comprehensive analysis of a novel control approach to improve the efficiency of parallel LLC resonant inverters using a combination of a current controlled variable inductor (VI) and phase shift (PS). The proposed control aims to reduce the Root Mean Square (RMS) current, thereby reducing conduction and switching losses, and improving power transfer efficiency, while considering zero-voltage-switching (ZVS) operation, output power variations and load changes. Furthermore, a design methodology for the variable inductor is proposed, and design considerations relevant to this application are discussed. The effectiveness of the proposed approach is evaluated through mathematical modeling and experimental results. The mathematical modeling results show that the proposed approach, utilizing SiC MOSFETs, maintains a maximum efficiency of 98.5% for a 20 kW inverter over a wider range of output power, which is a significant improvement over existing approaches. The experimental results also confirm the effectiveness of the proposed control in improving the efficiency of parallel LLC resonant inverters.

High Power Density Buck Boost DC/DC Converter Using SIC MOSFET

Abstract High power density is an advance in power electronics. Third generation wide-bandgap semiconductor devices (WBG SICs) offer significantly improved performance compared to standard silicon devices. SIC MOSFET is commonly used in power electronic equipment such as converters due to its low resistance, excellent thermal stability, and rapid switching speed. Increasing the switching frequency effectively reduces the circuit size. This article uses SIC MOSFET and STM32 single-chip MCU to design a high power density and higher frequency buck boost converter and establish a simulation model in LTspice. The driving circuit designed for SIC MOSFET is intended to maximize the converter’s reliability. Synchronous rectification applies to enhance the converter efficiency. Compared to other types of converters, the size of the converter is reduced, achieving the goals of lightweight and high power density of DC/DC converters.

Characterization of Threshold Voltage Shift in SiC MOSFETs Under Nanosecond-Range Switching and Its Impact on High- Frequency Applications

Characterization of Threshold Voltage Shift in SiC MOSFETs Under Nanosecond-Range Switching and Its Impact on High- Frequency Applications