SiC MOSFET Module Research Articles

Study on the influence mechanism of gate oxide degradation on DM EMI signals in SiC MOSFET

This paper investigates gate oxide degradation and its influence on Differential Mode(DM) EMI signals. The study reveals that changes in the parasitic capacitance within the chip, resulting from gate oxide degradation, can modify the amplitude-frequency characteristics of DM EMI signals, leading to unexpected transmission outcomes. This paper subjects SiC MOSFET modules to periodic high-temperature gate bias stress, extracts the spectrum characteristics of DM EMI, and assesses the impact of junction temperature. The analysis explores the impact of gate oxide degradation on low and high frequency DM EMI signals. Experimental results reveal distinct sensitivities of amplitude-frequency characteristics in the DM EMI signals to temperature variations and responses to gate oxide degradation at various frequency bands. The extrapolation of the correlation between the frequency-domain characteristics of the DM EMI signals and the degree of gate oxide degradation introduces a novel approach to evaluate the lifespan of power electronic devices.

Characterization of Electro-Thermal Coupling Behaviors and Safe Operating Area of SiC MOSFET Modules in Pulsed Power Applications

Characterization of Electro-Thermal Coupling Behaviors and Safe Operating Area of SiC MOSFET Modules in Pulsed Power Applications

Flexible Rogowski current probes in measurements of ultra-fast SiC MOSFET modules – limitations and challenges

Flexible Rogowski current probes in measurements of ultra-fast SiC MOSFET modules – limitations and challenges

Local Interconnection Degradation of a Double-Sided Cooling SiC MOSFET Module Under Power Cycling

Local Interconnection Degradation of a Double-Sided Cooling SiC MOSFET Module Under Power Cycling

A rapid-sintering Cu-Cu joints with ultrahigh shear strength and super reliability for power electronics package

Sintered Cu interconnection technology for power electronics has been widely investigated owing to its unique low temperature sintering high temperature service characteristics and price superiority. However, the currently research usually requires long sintering time (>30 min) and high pressure (>5 MPa). Here, we synthesized copper formate coated Cu nanoparticles (Cu-FA) by a solvothermal reaction, which can achieve rapid sintering at 260 °C with pressure of 5 MPa in 5 min to obtain robust joints of 67.41 MPa for fabricating SiC MOSFET devices. After 1000 h thermal aging and 1000 cycles thermal shock, the strength of joints can still maintained above 50 MPa. Moreover, SiC MOSFET modules were demonstrated using Cu-FA die attachment, which exhibit a 43.6 % lower thermal resistance compared to commercial Sn–Pb solder. Furthermore, copper paste performs better in long-term reliability. This paper provides an effective way to obtain high quality sintered Cu joints rapidly, which is suitable for the packaging of next generation power devices.

Measurement of Thermal Resistance of SiC MOSFET Module Based on Conduction Voltage Drop

Measurement of Thermal Resistance of SiC MOSFET Module Based on Conduction Voltage Drop

Reduced Overshoots, Oscillations and dV/dt Generation in Parallel Connected SiC MOSFET Modules with Optional Active Current Balancing

Reduced Overshoots, Oscillations and dV/dt Generation in Parallel Connected SiC MOSFET Modules with Optional Active Current Balancing

Active Gate Driver With the Independent Suppression of Overshoot and Oscillation for SiC MOSFET Modules

Active Gate Driver With the Independent Suppression of Overshoot and Oscillation for SiC MOSFET Modules

Competitive Failures Decoupling and Mechanisms Analysis of SiC MOSFET Module Under Power Cycling Stress

Competitive Failures Decoupling and Mechanisms Analysis of SiC MOSFET Module Under Power Cycling Stress

Modelling SiC MOSFET module threshold voltage (VTH) and impact of parallel device ΔVTH on short circuit robustness

In SiC modules, where several power MOSFETs are connected in parallel for high current conduction capability, the issue of threshold voltage (VTH) variation between individual devices can become problematic. In instances where the standard deviation of device VTH is minimized by appropriate VTH pre-screening, non-uniform VTH shift under bias-temperature-instability can lead to increased VTH dispersion and potentially poor current sharing. Although non-destructive for normal operation, VTH dispersion in surge events like short circuits can cause premature module failure. In this paper, experimental investigations backed by theoretical models have been developed to explain the relationship between device VTH dispersion and module VTH shift. This is done for Si and SiC MOSFETs. Five Si/SiC MOSFETs are paralleled in a custom printed-circuit-board allowing individual VTH and module VTH measurements. It is shown that the module VTH is typically between the smallest VTH and the mean VTH, depending on the VTH standard deviation. Using empirical models for MOSFETs in weak inversion derived from the measured subthreshold gate transfer characteristics, the model can estimate module VTH from a dispersion of individual MOSFET VTH. It can also predict the impact of non-uniform VTH shift between constituent devices on the overall module VTH. Finally, the impact of VTH mismatch on current sharing during short circuits in parallel connected SiC MOSFETs is presented. The results show that VTH mismatch in parallel connected SiC MOSFETs reduces the short circuit withstand time from 5 μs to 4.5 μs compared to VTH matched SiC MOSFETs.

Non‐contact and anti‐interference diagnosis of SiC MOSFET module bond wire faults for EV wireless charging device

AbstractSiC MOSFET modules are widely used for bidirectional wireless charging of electric vehicles. However, prolonged use can result in bond wire faults, leading to reliability issues. To address this problem, a non‐contact bond wire monitoring method that can be carried out using the charging coil of the wireless charging device is proposed. Here, two monitoring loops are constructed based on the circuit topology, and their impedance magnitudes are measured on the charging coil to avoid the influence of battery voltage on monitoring results. To detect the bond wire condition, the impedance magnitude difference of the two monitoring loops is chosen as an indicator, which is very sensitive to the bond wire lift‐off. However, the monitoring results may be influenced by the aging of resonant capacitors and the offset of the charging coil. In particular, the influence of the coil offset is significant. To mitigate this effect, a prognostic parameter calibration method is proposed. Experimental results confirm the effectiveness of the proposed method, which provides a promising solution for the reliable and safe operation of SiC MOSFET modules in wireless charging devices.

Junction temperature estimation of a SiC MOSFET module for 800V high-voltage application in electric vehicles

Junction temperature estimation of a SiC MOSFET module for 800V high-voltage application in electric vehicles

Integration of SiC Devices and High-Frequency Transformer for High-Power Renewable Energy Applications

This paper presents a novel structure of Integrated SiC MOSFETs with a high-frequency transformer (I-SiC-HFT) for various high-power isolated DC–DC converters. Several resonant converters are considered for integration in this paper, including the phase-shift full-bridge (PSFB) converter, inductor–inductor–capacitor (LLC) resonant converter, bidirectional PSFB converter, and capacitor–inductor–inductor–capacitor (CLLC) resonant converter. The applications of I-SiC-HFT are focused on V2G EV battery charging systems, energy storage in DC and AC microgrids, and renewable energy systems. SiC devices, including MOSFETs, Schottky diodes, and MOSFET modules, are used in this novel structure of I-SiC-HFT. The high-frequency magnetic structure uses distributed ferrite cores to form a large central space to accommodate SiC devices. The optimized architecture of I-SiC-HFT and heatsink structure is proposed for thermal management of SiC devices. To prove the concept, a small-scale 1.5 kW prototype I-SiC-HFT is used to demonstrate the basic structure and various performance indicators through the FEM based electromagnetic simulation and DC–DC converter experiments.

An Active Gate Driver of SiC MOSFET Module Based on PCB Rogowski Coil for Optimizing Tradeoff Between Overshoot and Switching Loss

The superior characteristics of the silicon carbide metal-oxide-semiconductor field-effect transistor (SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) allow its wide use for improving the efficiency and power density of power electronic systems. However, the higher switching speed exacerbates the problems of overshoot, oscillation, and electromagnetic interference (EMI), which need to be properly addressed. In this article, a novel stage-detection closed-loop active gate driver (AGD) based on the printed-circuit-board (PCB) Rogowski Coil is proposed for optimizing the switching performance of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. And its stage identification threshold design can weaken the influence of the varying nonlinear parameters, especially for the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process. First, the gate driver trajectory and the switching process of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are analyzed. The optimal driver parameter dynamic configuration among the existing stage-control schemes is defined and unified, which aims to optimize the tradeoff between the overshoot and switching loss. Then, the parameter design of the PCB Rogowski Coil is illustrated. And the operation principle and working process of the proposed AGD are introduced. Finally, the performance of the proposed AGD and the effectiveness of the stage-control schemes are verified in the double-pulse test under different conditions. The experimental results show that the proposed AGD can not only reduce the overshoot and suppress the oscillation but also optimize the compromise of the switching loss and switching time.

Performance limits of high voltage press-pack SiC IGBT and SiC MOSFET devices

Considering the switching frequency limit and electromagnetic interference, the selection of high voltage SiC IGBT and SiC MOSFET is confusing due to punch-through effect and bipolar characteristics of SiC IGBT. The thermal resistance, static characteristics and dynamic characteristics of SiC IGBT and SiC MOSFET module with Press-Pack packaging are measured to evaluate the switching frequency limit and electromagnetic interfere of them. The tradeoffs of SiC IGBT between switching frequency limit and electromagnetic interfere are less attractive due to the intrinsic characteristics, such as high power loss and punch-through effect. The possible solutions for SiC IGBT are proposed based on the improvement of driving resistor and driving voltage.

Optimization Design of Packaging Insulation for Half-Bridge SiC MOSFET Power Module Based on Multi-Physics Simulation

With the development of power modules for high voltage, high temperature, and high power density, their size is becoming smaller, and the packaging insulation experiences higher electrical, thermal, and mechanical stress. Packaging insulation needs to meet the requirement that internal electric field, temperature, and mechanical stress should be as low as possible. Focusing on the coupling principles and optimization design among electrical, thermal, and mechanical stresses in the power module packaging insulation, a multi-objective optimization design method based on Spice circuit, finite element field numerical calculation, and multi-objective gray wolf optimizer (MOGWO) is proposed. The packaging insulation optimal design of a 1.2 kV SiC MOSFET half-bridge power module is presented. First, the high field conductivity characteristics of the substrate ceramic and encapsulation silicone of the packaging insulation material were tested at different temperatures and external field strengths, which provided the key insulation parameters for the calculation of electric field distribution. Secondly, according to the mutual coupling principles among electric–thermal–mechanical stress, the influence of packaging structure parameters on the electric field, temperature, and mechanical stress distribution of packaging insulation was studied by finite element calculation and combined with Spice circuit analysis. Finally, the MOGWO algorithm was used to optimize the electric field, temperature, and mechanical stress in the packaging insulation. The optimal structural parameters of the power module were used to fabricate the corresponding SiC MOSFET module. The fabricated module is compared with a commercial module by the double-pulse experiment and partial discharge experiment to verify the feasibility of the proposed design method.

A 200 kW high‐efficiency and high‐power density xEV motor controller based on discrete SiC MOSFET devices

AbstractAs one significant component of the Electric‐Driven System of xEV (all types of electric vehicles), motor controllers have been widely applied and researched. However, the performance of controllers based on Si IGBT is limited due to the characteristics of semiconductors, while the volume and weight of SiC MOSFET modules limit the power density of controllers. Therefore, a scheme for motor controllers based on paralleled discrete SiC MOSFET devices is exhibited in this paper. First, the paper analyzes the current sharing problem of paralleled devices, which is a critical problem limiting the efficiency and power density of the controller. Furthermore, according to the analysis results, a comprehensive optimized scheme for motor controller design is proposed from three aspects of device parameter selection, circuit symmetrical layout, and spatial structure design. The design effectively improves the power density and efficiency of the controller. Finally, this paper carries out simulation analysis and mechanical back‐to‐back tests based on an actual prototype, verifying the effectiveness of the proposed scheme. The test results show that the rated power of the motor controller is up to 200 kW, the power density is more than 50 kW/L (and 50 kW/kg), and the peak efficiency is up to 99.3%.

Characterization and Modeling of SiC MOSFET Modules for High-voltage Applications

This paper presents a detailed characterization and modeling of 6.5kv SiC MOSFET half-bridge module. Based on the equivalent circuit topology, the model parameters are extracted from the data manual and test data, and the behavior model is constructed to describe the static and dynamic characteristics of the device. This paper used behavioral model functions, and carries out parameter extraction and model fitting for new devices. The model is verified by double pulse test under inductive load. The verification results show that the modeling work is correct and effective, it can predict the switching performance of devices in high voltage applications.

철도차량 전동기 드라이빙 효율 증대를 위한 SiC 전력용 반도체 기반의 2레벨 3상 인버터의 손실 특성 비교

The purpose of this paper is to compare and analyze the loss of propulsion inverter using SiC and Si power semiconductors for high efficiency of railway vehicles with renewable energy. Accordingly, loss comparison and analysis were carried out through PSIM Thermal Module and Loss Modeling with a SiC-MOSFET module and Si-IGBT Module. As a result, 2-level 3phase inverter using SiC-MOSFET module had extremely low switching loss compared to propulsion inverter that using Si-IGBT module. If SiCMOSFET module is used in propulsion inverter of traction motor for railway vehicles, it is considered to be advantageous for high efficiency.

Effect of common branch impedance coupling and mutual inductance on current sharing of paralleled SiC MOSFETs with different layouts

Overcurrent failure caused by imbalanced current distribution is one of the universal failure forms of the SiC MOSFET module. The current sharing of parallel SiC MOSFETs is an important guarantee for the safe and reliable operation of parallel devices even the whole system. The existence of current coupling has a significant influence on the current sharing among paralleled SiC MOSFETs. Here, the mechanism of dynamic and static current imbalance under the different layouts resulting from current coupling generated by common branch impedance coupling and mutual inductance is comprehensively investigated by theoretical analysis and simulation validations. It is concluded that dynamic current imbalance is more serious when the drain confluence point and power source confluence point are on both sides than they are on the one side. While, the influence of the arrangement of two confluence points on the static current distribution is in reverse. Finally, a flexible and adjustable test bench is designed to verify the current sharing performance on the different layouts. The experimental results validate the correctness of the theoretical analysis. Based on these results, some guidelines are provided for the parallel-connected application of SiC MOSFETs.