SiC MESFET Research Articles

Improved 4H–SiC MESFET with recessed and multi-concentration doped channel

In this paper, the 4H–SiC metal semiconductor field effect transistor with symmetric lightly doped drain (SLDD-MESFET) is improved and a 4H–SiC MESFET with recessed and multi-concentration doped channel (RMDC-MESFET) is proposed. According to the 2-D simulation results, it is found that compared with the SLDD structure, the saturation current of RMDC-MESFET is increased from 373 mA/mm to 480 mA/mm, which is 29% higher. The breakdown voltage remains stable, resulting in a 25% increase in maximum output power density, from 5.89 W/mm to 7.34 W/mm. At the same time, the transconductance of the proposed structure is increased by 28% from 68 mS/mm to 87 mS/mm, resulting in an 18% increase in the cut-off frequency from 21.45 GHz to 25.3 GHz. The DC and RF performances of the RMDC-MESFET are improved simultaneously, so the structure has good prospects for high-power and RF applications.

Improved 4H–SiC MESFET with bulgy channel

This paper proposes an improved 4H–SiC metal semiconductor field effect transistor with a bulgy channel (BC-MESFET) whose gate-source and gate-drain drift regions are shifted downward 0.1 μm relative to the channel below the gate. By introducing recesses at both ends of the metal gate, both the DC and AC characteristics of the structure have been greatly improved. The simulation results show that the saturation current of BC-MESFET is 30% higher than that of DR-MESFET, and the breakdown voltage is 78% higher. Therefore, the maximum output power density has a significant increase of 137%. In terms of RF, since the gate-source capacitance of the BC-MESFET structure is 31% lower than that of the DR-MESFET, its characteristic frequency is also improved by 18%. In this paper, aiming at high power added efficiency (PAE), the bump height H of the buffer layer under the lower gate is optimized, and a structure with 25% higher PAE than DR-MESFET is obtained.

A novel 4H–SiC MESFET with P-type doping zone and recessed buffer layer

Based on the double recessed 4H–SiC metal semiconductor field effect transistor (DR-MESFET) structure, a new 4H–SiC MESFET with p-type doping zone in drain drift region and recessed buffer layer under the source drift region (PDRB-MESFET) is proposed in this paper. The simulation results show that the breakdown voltage of this novel structure is improved by 63.76% compared with that of DR-MESFET. Thus, the maximum output power density of the device is increased by 72.85%. As for RF, the cutoff frequency decreases by 4.42% due to the increase of gate source capacitance, and RF performance deteriorates slightly. But in general, it is meaningful to exchange a slight decline in RF performance for a significant improvement in DC performance. The length and width of the p-type doping region are optimized and the optimal size of the p-type doping region is obtained.

Modelling of High Frequency SIC MESFET for Optical Sensing Applications

The analysis and design of fabricated optical GaAs high frequency MESFET model was improved and also majority carrier concentration doping is improved in un flatted channel region. This result was proved with component of photo sensors. The diode voltage is produced at the metal semi conductor rectifying contact and its blocks current flow in one polarity of voltage. The Laplace’s equation is used to solve problematically under the absence of light in a place and interpretation state. This paper main intention is to develop the MESFET using the finite differences method and solve the under illumination. The simulation responses main improvement is bunch of charge particles in optical device, the channel charge particles are varied at various operating voltages and light and also the simulation result was plotted in X and Y direction respect of electric field. In here the simulated and plotted results was analyzed the optical component is purely affected with intensity of illumination.

Silicon Carbide Technology of MESFET-Based Power Integrated Circuits

This paper presents the start development of a design kit for an innovative technology based on the same lateral topology and the same substrate, which is a dual-gate SiC MESFET. From the electrical characteristic of an initial dual-gate MESFETs, a SPICE model of this device has been established. This model allows developing by simulating a design kit of three devices, which are, respectively, a signal MESFET, a buffer MESFET, and a power MESFET. The signal MESFETs are dedicated to the signal command shaping. The buffer MESFETs would be used as current buffer in the driver circuit for supplying the gate electrode of the power switches. The power MESFETs would be used as power switches. The electrical measurements validate the feasibility of this technology. The characterizations have shown that the technology is operational, and the three devices present the considered electrical behavior. The contact resistance technology must be improved for optimizing the electrical performances. The devices will be used for the design of electronic functions (e.g., ring oscillator and totem pole) in the purpose to consider a full integrated driver in SiC, which could operate in harsh environments.

Assessment of intrinsic small signal parameters of submicron SiC MESFETs

In this paper, a technique has been developed to estimate intrinsic small signal parameters of submicron SiC MESFETs, designed for high power microwave applications. In the developed technique, small signal parameters are extracted by involving drain-to-source current, Ids instead of Schottky barrier depletion layer expression. It has been demonstrated that in SiC MESFETs, the depletion layer gets modified due to intense transverse electric field and/or self-heating effects, which are conventionally not taken into account. Thus, assessment of AC small signal parameters by employing depletion layer expression loses its accuracy for devices meant for high power applications. A set of expressions for AC small signal elements has been developed using Ids and its dependence on device biasing has been discussed. The validity of the proposed technique has been demonstrated using experimental data.

Reply to the “comments on -a theoretical study on the linearity of the Id-T curve of a SiC MESFET for sensor application”

In this paper, a reply to a to a recent article entitled “Comments on A-theoretical study on the linearity of the Id-T curve of a SiC MESFET for sensor application” is given which opines that the functional form of built-in-potential of a metal-semiconductor junction is considered erroneously in the original publication. On the contrary to the comment, this article justifies the original work with suitable logic and supportive references.

Impact of parasitic resistances on the electrical characteristics of a SiC MESFET

The mathematical formulations of extrinsic resistances of a SiC-MESFET are developed and their impact on the electrical characteristics of the device has been studied in this work. Numerical techniques are used to calculate the drain current of a MESFET considering the existence of parasitic resistances. The analytical expressions of drain conductance, mutual conductance and cut off frequency of the device have been derived and their variations over different device parameters are studied incorporating the effect of extrinsic resistances. It is observed that the impact of parasitic resistances on the drain current and other parameters of the device is significant and device performance usually degrades with parasitic resistances. The parasitic resistances computed using our approach is compared with the experimentally extracted data reported earlier and a reasonably good agreement has been observed.

Comments on “A theoretical study on the linearity of the Id-T curve of a SiC MESFET for sensor application”

In this article, the validity of the formulation presented in a recent paper has been questioned. It is pointed out that the built-in potential at the gate of a metal-semiconductor field effect transistor has been erroneously considered, as a result of which the related mathematical formulations and calculations presented in the paper become invalid.

An improved model for the $${I{-}V}$$ I - V characteristics of submicron SiC MESFETs by evaluating the potential distribution inside the channel

This paper presents a detailed mathematical model describing the $$I{-}V$$ characteristics of submicron SiC MESFETs. Poisson’s equation with appropriate boundary conditions has been solved to determine the potential distribution inside the channel. The location ( $$L_1$$ ) of the Schottky barrier gate with a corresponding depletion layer width ( $$u_1$$ ) where the carrier’s velocity gets saturated has been evaluated. It has been demonstrated that, both $$L_1$$ and $$u_1$$ are bias dependent, and their values change by changing the drain biasing even after the onset of current saturation. This causes a modification in the depletion layer underneath the Schottky barrier gate and, thus, changes the available channel cross-section for the flow of current. It has been shown that finite output conductance in the saturation region of operation, which is usually observed in submicron devices, can be explained with Schottky barrier depletion layer modification. The $$I{-}V$$ characteristics of submicron SiC MESFET are modeled and compared with conventional velocity saturation techniques, where the depletion layer after the onset of current saturation has been treated as a constant. It is observed that the proposed technique gave $$\sim $$ 15.9% improvement in the modeled characteristics of a submicron SiC MESFET.

Frequency performance of a SiC MESFET with a moderately doped buffer layer

ABSTRACTIn this work, we study the impact of a moderately doped P buffer layer below N-type active channel of a Silicon Carbide Metal Semiconductor Field Effect Transistor (SiC MESFET)​​​​​ on its frequency performance. The effect of depletion layer width in the channel developed at the channel–buffer junction has been investigated assuming two separate field regions under the gate. An improved method to calculate mutual and drain conductance of the device is suggested for conventional two-region model. The cut-off frequency and maximum frequency of the device have been calculated and their variations over buffer layer doping density have been presented. The theoretically calculated values of cut-off frequency and maximum frequency of the device have been compared with the experimental value reported earlier and a considerably good agreement has been observed.

A theoretical study on the linearity of the Id-T curve of a SiC MESFET for sensor application

This theoretical study includes the impact of ambient temperature fluctuations on the drain current of a SiC MESFET considering two field regions under the gate at a considerably high drain field. The variations of drain current of the device with ambient temperature are studied and the sensitivity of the device with temperature is calculated. An analytical expression of temperature sensitivity of the device is derived for a MESFET operating under the two region model. The variations of device sensitivity with temperature are presented for different gate length and applied biases. The results show that the linearity of drain current over ambient thermal variation improves for proper biasing conditions of gate and drain terminals and selection of appropriate gate length. Moreover, an effort has been made to compare our work with an experimentally observed data reported earlier.

An improved model for current voltage characteristics of submicron SiC MESFETs

This paper presents an improved model to simulate I-V characteristics of submicron SiC MESFETs, designed for microwave power applications. The proposed model adequately addresses a non-ideal Schottky behavior, commonly observed in submicron devices, by adjusting the device biasing through simulation variables. Swarm optimization technique has been applied to investigate gate length (Lg) dependent performance of various SiC MESFETs models. It has been found that the proposed model provides an improved accuracy, ranging from 7% to 24%, compared to the best models available in the literature. This enhanced performance is primarily associated with the extra control, provided by the proposed model to simulate the movement of the depletion region in the channel as a function of applied voltages. An attempt has been made to identify the location underneath the Schottky barrier gate, where the depletion region gets its maximum height and thus controls the saturation current of the channel. Physical and electrical parameters of various SiC MESFETs having Lg=0.4μm, 0.5μm, 0.6μm and 0.7μm have also been assessed. An accurate assessment of the physical parameters of the device exhibits the validity of the model for submicron SiC MESFETs.

Improved multi-recessed 4H–SiC MESFETs with double-recessed p-buffer layer

An improved multi-recessed 4H–SiC metal semiconductor field effect transistor (MRD-MESFET) with double-recessed p-buffer layer (DRB-MESFET) is proposed in this paper. By introducing a double-recessed p-buffer layer, the gate depletion layer is further modulated, and higher drain saturation current and DC transconductance are obtained compared with the MRD-MESFET. The simulations show that the drain saturation current of the DRB-MESFET is about 42.4% larger than that of the MRD-MESFET. The DC transconductance of the DRB-MESFET is almost 15% higher than that of the MRD-MESFET and very close to that of double-recessed structure (DR-MESFET) at the bias conditions of Vgs=0V and Vds=40V. The proposed structure has an improvement of 26.1% and 74.2% in the output maximum power density compared with that of the MRD-MESFET and DR-MESFET, respectively. In the meanwhile, the proposed structure possesses smaller gate-source capacitance, which results in better RF characteristics.

Failure analysis of ESD-stressed SiC MESFET

Reliability studies are required for SiC device development. In a previous work we studied the intrinsic ESD robustness of a SiC MESFET. The failure mechanism was related to the triggering of an NPN parasitic transistor. In this work, a new MESFET layout is considered, which optionally include a Zener diode for internal protection. TLP testing and failure analysis has been carried out. Two new failure mechanisms are evidenced. Based on this knowledge, solutions are proposed to further improve the ESD robustness.

Comprehensive study of a 4H–SiC MES–MOSFET

In this paper, we studied the enhancement of the breakdown voltage in the 4H–SiC MESFET–MOSFET (MES–MOSFET) structure which we have proposed in our previous work. We compared this structure with Conventional Bulk-MOSFET (CB-MOSFET) and Field plated Conventional Bulk-MOSFET (FCB-MOSFET) structures. The 4H–SiC MES–MOSFET structure consists of two additional schottky buried gates which behave like a Metal on Semiconductor (MES) at the interface of the active region and substrate. The motivation for this structure was to enhance the breakdown voltage by introducing a new technique of utilizing the reduced surface field (RESURF) concept. In our comparison and investigation we used a two-dimensional device simulator. Our simulation results show that the breakdown voltage of the proposed structure is 3.7 and 2.9 times larger than CB-MOSFET and FCB-MOSFET structures, respectively. We also showed that the threshold voltage and the slope of drain current (ID) as a function of drain–source voltage (VDS) for all the structures is the same.

Improved performance of 4H–SiC MESFETs with Γ-gate and recessed p-buffer layer

An improved 4H–SiC MESFET with Γ-gate and recessed p-buffer layer (ΓRP-MESFET) is proposed in this paper. The channel electric field and the gate depletion layer have been modulated by utilizing Γ-gate and introducing recessed p-buffer layer simultaneously in the ΓRP-MESFET structure. The simulated results show that the drain saturation current and the breakdown voltage of the proposed structure are about 18.5% and 19.4% larger than those of the double recessed structure (DR-MESFET), respectively. Therefore, the maximum output power density of 8.17W/mm can be achieved, which is about 42% higher than that of the reported one. The cut-off frequency (fT) of the proposed structure is 19.8GHz, which is higher than that of the conventional structure due to its smaller gate–source capacitance (Cgs).

Analysis of an ESD failure mechanism on a SiC MESFET

Efficient energy management become more and more crucial with increasing energy resource scarcity. Power electronic will play a major role in this field and thus require innovations like using wide band gap semiconductor to build power devices. SiC, GaN, diamond material-based devices are currently more or less mature and will sooner or later require investigations on their reliability to allow their wide adoption. In this work we investigate on the robustness of a SiC-MESFET to ElectroStatic-Discharge (ESD). Surprisingly the ESD robustness is rather low and found to be related to both current non-uniformity and a quite unexpected parasitic NPN bipolar transistor triggering. The outcome of this study allows proposing first guidelines to optimize ESD robustness of such devices.

Monolithic Integration of Power MESFET for High Temperature SiC Integrated Circuits

This work provides experimental result on fabricated 4H-SiC lateral power MESFET intended to be used in further development of high temperature integrated circuits for power application. The power SiC MESFET device was developed using a planar technology on silicon carbide and P implant isolation technique. Its destination to monolithic integration demands a lateral layout connection topology. The use of quite high doped N type epitaxial layer (1017cm-3) typical for the integrated circuits raises difficulties to keep the leakage current of the Schottky gate in a decent range. Therefore, a hexagonal close loop gate in conjunction with three metal interconnection levels was adopted, thus obtaining a compact lateral MESFET device and avoiding any drain to source parasitic leakage path. Using the tungsten gate MESFETS, the first generation of monolithic integrated lateral power MESFET device was integrated on the same wafer with digital circuits and a voltage reference analog circuit able to operate up to 250C. The temperature range can be next improved by using higher barrier for the gate contact.

S-Band 300 W Output SiC MESFET

High power internally-matched 4H-SiC MESFET with a total gate width of 4×27mm was demonstrated. The double p-type buffer layers were used for preventing electrons from entering the buffer and reaching the substrate traps. The peak of the electric field in the edge of the gate is restrained by the double recess gate structure, which is advantageous to the high break down voltage. A thermal oxide layer was grown and subsequently etched to remove etch-induced damage. The ohmic contact resistivity of 2 ×10-6Ω•cm2 was achieved. The pulsed output power, gain and drain efficiency of the internally-matched 4x27mm SiC MESFET measured at 2GHz were 300W, 9.2dB, and 24.8%, respectively.