SiC Junction Field Effect Transistor Research Articles

Short-Circuit Failure Mechanisms of 650-V GaN/SiC Cascode Devices in Comparison With SiC MOSFETs

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad.

Dv/Dt-Control of 1200-V Normally-off SiC-JFET/GaN-HEMT Cascode Device

A normally- off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (i.e., 1200 V) SiC junction field effect transistor (JFET) and a low-voltage GaN high electron mobility transistor (HEMT). This cascode device exhibits superior thermal stability and switching performance compared to the SiC MOSFETs, but also inevitably presents challenge in dv/dt -control as the input gate does not directly control the high-voltage JFET. Since dv/dt -control is of great importance to the management and suppression of electromagnetic interference in power electronics systems, methods of controlling the dv/dt rates of SiC/GaN cascode devices need to be developed. In this article, we conduct systematic investigation on different dv/dt control schemes with theoretical analysis and experimental evaluation. A dv/dt -control method based on diode-clamped external JFET gate resistor is proposed and evaluated by comparing it with other more conventional methods. The proposed dv/dt -control method is verified to provide a balanced dv/dt -control on the device turn- on and turn- off .

Three-Terminal Si/SiC Hybrid Switch

A Si/SiC hybrid switch is an innovative power semiconductor switch realized by paralleling a Si insulated-gate bipolar transistor (IGBT) and a SiC device (metal-oxide semiconductor field-effect transistor ( mosfet ) or junction field-effect transistor). The Si/SiC hybrid switch combines advantages of Si IGBT's high conduction capability and SiC device's fast switching speed, and effectively addresses Si IGBT's high turn- off loss issue and SiC mosfet 's high cost concern. However, to control the hybrid switch, two separate gate drivers are usually needed, which increases the complexity and cost. In this letter, a simple and effective gate driver circuit is designed for the Si/SiC hybrid switch, which requires only one control signal and gate driver circuit to drive both Si IGBT and the SiC device, making the hybrid switch a typically three-terminal device. The operation principles and design guidelines are presented and analyzed. A three-terminal 1200-V, 200-A hybrid switch prototype in a half-bridge configuration is developed and experimental results verify its effectiveness.

Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions

Prolonged Venus surface missions (lasting months instead of hours) have proven infeasible to date in the absence of a complete suite of electronics able to function for such durations without protection from the planet’s extreme conditions of ~460°C, ~9.3 MPa (~92 Earth atmospheres) chemically reactive environment. Here, we report testing data from a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber. These results extend the longest reported duration of electronics operation in Venus surface atmospheric conditions almost threefold and were accomplished using prototype SiC JFET chips of more than sevenfold increased complexity. The demonstrated advancement marks a significant step toward realization of electronics with sufficient complexity and durability for implementing robotic landers capable of returning months of scientific data from the surface of Venus.

Demonstration of 4H-SiC Digital Integrated Circuits Above 800 °C

Short-term demonstrations of packaged 4H-SiC junction field-effect transistor (JFET) logic integrated circuits (ICs) at temperatures exceeding 800 °C in air are reported, including a 26-transistor 11-stage ring oscillator that functioned at 961 °C ambient temperature believed unprecedented for electrical operation of a semiconductor IC. The expanded temperature range should assist temperature acceleration testing/qualification of such ICs intended for long-term use in applications near 500 °C ambient, and perhaps spawn new applications. Ceramic package assembly leakage currents inhibited the determination of some intrinsic SiC device/circuit performance properties at these extreme temperatures, so it is conceivable that even higher operating temperatures might be obtained from SiC JFET ICs by employing packaging and circuit design intended/optimized for T $\ge800$ °C.

Channel width effect on the operation of 4H-SiC vertical JFETs

SiC JFETs may have the lowest overall losses of switching devices and can operate at temperatures over 400 °C. Over different junction field-effect transistor (JFET) designs, the trenched and implanted (TI) gate vertical JFET (TI-VJFET) is very attractive since it may have the lowest on-resistance and its fabrication does not require epitaxial overgrowth or multiple angled implantation. 4H-SiC TI-VJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. Different design factors, including channel width, channel length, and mesa height, are considered. The effect of the channel geometry on the electrical characteristics has been studied by varying their width (1.5–5 µm). The specific ON resistance (RON) of the fabricated devices, at VGS = 0 V, varied from 12.5 to 6.2 mΩ cm2 with increasing the channel width. The effect of the channel width was more tremendous on the breakdown voltage of the transistors passing from 80 to 500 V, showing the importance of the static-induction effect (saddle point potential influenced by drain potential) on the transistor blocking characteristics. Indeed, the blocking voltage gain is varying from 50 to single digit values when increasing the channel width. The physical reason is that the blocking gain to first order depends exponentially on the channel dimensions as the drain-source current is exponentially related to the saddle point potential.

Suitability of N-ON Recessed Implanted Gate Vertical-Channel SiC JFETs for Optically Triggered 1200 V Solid-State Circuit Breakers

A requirement for the commercialization of power SiC transistors is their long term reliable operation under the hard-switching conditions and high temperatures encountered in the field. Normally ON 1200 V vertical-channel implanted-gate SiC junction field effect transistors (JFETs), designed for high-power bidirectional (four quadrant) solid-state-circuit-breaker (SSCB) applications, were repetitively pulse hard switched at 150 °C from a 1200 V blocking state to an ON-state current of 115 A, which is in excess of 13 times the JFET’s 250-W/cm2 rated current at 150 °C. The JFETs were fabricated in seven photolithographic levels with a single masked ion-implantation forming the p+ gates and guard rings, and with no epitaxial regrowth. The pulsed testing was performed using a low inductance $RLC$ circuit. In this circuit, energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard-switch stressing included over 2.4 million 1200 V/115-A hard-switch events at 150 °C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard-switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/ $\mu \text{s}$ and the pulse full width at half maximum (FWHM) was $1.8~\mu \text{s}$ . After over 2.4 million hard-switch events at 150 °C, the JFET blocking voltage characteristics remained unchanged while the ON-state conduction slightly improved, which indicate reliable operation. An optically triggered SSCB, based on these rugged JFET, is proposed.

Power Electronic Converters and Systems: Frontiers and Applications [Book News

Future power electronics will be dependent on recent silicon carbide power semiconductor devices like SiC metal oxide field effect transistor (MOSFET), SiC insulated gate bipolar transistor (IGBT), and SiC junction field effect transistor (JFET), capable of up to 15 kV hold-off voltages. Compared to silicon (Si), SiC-based power-switching devices present much lower leakage currents, higher blocking voltages, higher operating temperatures, lower on-state voltage drops, higher switching frequency, and higher thermal conductivity. These advanced semiconductor devices integrated within smart power electronic modules can be used to build advanced power converters such as multi-input, multiport converters; modular multilevel cascaded converters (MMCCs); and matrix, Z-source, and Y-source converters. Up-to-date electronic power conversion is priceless for applications like permanent magnet synchronous motor (PMSM) drives, induction motor (IM) drives, renewable energy systems (wind, photovoltaic), energy storage, fuel cells, and electrical vehicles (EV). Power electronic conversion is also the core of modern shipboard power systems, more electric aircrafts, flexible ac power transmission systems, distributed generation (DG) and microgrids, uninterruptible power supplies (UPS), and wireless power transfer (WPT). Assuming the reader is already familiar with the fundamentals of power semiconductors1], electronic power converters, and their control, this book explores and suggests new trends and frontiers in the interdisciplinary field of power electronics systems (PES). In includes contributions from an international panel of 44 PES experts covering subjects such as SiC devices, multilevel and matrix converters (MC), smart power electronic modules, zero voltage switching (ZVS) and zero current switching (ZCS), switching power supplies, EVs, sliding mode and intelligent direct torque control (DTC) of IM drives, sliding mode observers, and model-based predictive control (MPC) of PMSM drives and wind turbines (WTs). The book is also matchless in performing detailed study of contactless power (WPT) and in sequence-based control (SBC) together with the implementation of high-frequency solid-state power transformer (SST) using three-level neutral point clamped multilevel converters built with 15 kV SiC IGBTs. The book is divided in two parts and 20 chapters. It includes preface, table of contents, index, and references at the end of each chapter.

600-V 27-mΩ normally off SiC junction field effect transistors for high-efficiency power supply

Normally-off SiC junction field effect transistors (JFETs) with high blocking voltage and low gate leakage current were developed by localized current-path doping (LCD). Numerical simulation of electric field revealed that LCD effectively decreases the on-resistance of SiC JFETs without degrading blocking voltage. On the basis of the obtained simulation results, 600-V 27-mΩ normally off SiC JFETs were fabricated by LDC. The gate leakage current of the fabricated JFETs was suppressed by surface oxynitridation. By applying in a server power supply, we found that these improved JFETs decreased power loss due to FETs by 66%.

Boost Converter With SiC JFETs: Comparison With CoolMOS and Tests at Elevated Case Temperature

The emergence of hybrid electric vehicles (HEVs) has driven an increasing demand for high power densities in power converters. Silicon carbide (SiC) is a candidate of choice to meet this demand, and it has, therefore, been the object of a growing interest over the past decade. The boost converter (step-up converter) is an essential part of the typical powertrain of an HEV. This paper presents a scaled experiment in which a boost converter with a SiCjunction field-effect transistor is compared to the same converter with a silicon (Si) superjunction metal oxide semiconductor field-effect transistor (MOSFET). In a first part, classic heatsinks are used; in a second part, the case of the transistors is maintained at 105 $^{\circ}$ C to mimic a cooling by radiator water. In both cases, results show a clear advantage for SiC.

On-State and Switching Performance Comparison of A 600 V-Class Hybrid SiC JFET and Si Superjunction MOSFETs

We compare the on-state and switching performance of a 600 V-class Hybrid SiC junction field effect transistor (HJT) and Si superjunction MOSFETs (SJ-MOSs), both of which are packaged in TO-3P full-mold package, as a function of operating frequency. The maximum load current is limited by the package power dissipation rating determined by the maximum junction temperature. Since the HJT is composed of a SiC JFET and a low voltage Si MOSFET, the allowable maximum junction temperature of the HJT is the same as that of SJ-MOSFETs, namely 150 °C. The experimental results show that the maximum operating current of the HJT is comparable to that of SJ-MOSs, but the EMI noise of the HJT is much suppressed due to lower dV/dt.

Design Steps Toward a 40-kVA SiC JFET Inverter With Natural-Convection Cooling and an Efficiency Exceeding 99.5%

This paper describes the concept, design, construction, and experimental investigation of a 40-kVA inverter with silicon carbide junction field-effect transistors (JFETs). The inverter was designed to reach an efficiency exceeding 99.5%. The size of the heat sink is significantly reduced in comparison to silicon insulated-gate bipolar transistor designs, and the high efficiency makes it possible to use free-convection cooling. This could potentially increase reliability compared with solutions with fans. A very low conduction loss has been achieved by parallel connecting ten 85-mΩ normally-ON JFETs in each switch position. A special gate-drive solution was applied, forcing the transistors to switch very fast (approximately 10 kV/μs), resulting in very low switching losses. As output power is almost equal to input power, special effort was done to precisely determine the amount of semiconductor power losses via comparative thermal measurements. A detailed analysis of the measurements shows that the efficiency of the inverter is close to 99.7% at 40 kVA.

Silicon Carbide Power Modules for High-Temperature Applications

A hermetic multichip power package for silicon carbide devices that will operate at 200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C ambient and switch 50-100 A has been developed. The Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /MoCu structure, in which the SiC junction field-effect transistors and diodes are attached, was designed to hermetically seal the device areas. Details of the materials and processes used to fabricate the package are discussed. Die attach, ribbon bonding, and lid attach, as well as thermal modeling, electrical testing, and thermal cycling results are also described.

Model for Power SiC Vertical JFET With Unified Description of Linear and Saturation Operating Regimes

A novel SiC junction field-effect transistor (JFET) model that uses a unified description of linear and saturated conduction modes is proposed. Advantages of the proposed model are improved robustness and convergence, inclusion of field-dependent mobility effects, and more physical description of the current saturation phenomenon. The model is validated against a normally off JFET sample over a wide temperature range. Finite-element simulations are used to demonstrate the physics-based nature of the proposed model.

Power characteristics of SiC bipolar-mode JFET

The operational mechanism of normally-off type bipolar-mode SiC junction field effect transistor (BJFET) is studied by using a two-dimensional numerical model. Compared with the unipolar-mode SiC JFET, the bipolar-mode can reduce the on-state resistor of the SiC JFET effectively and compromise between the on-state and off-state characteristic of the device. The simulation resluts also show that switching time of BJFET increases remarkably.

A Physics-Based Model for a SiC JFET Accounting for Electric-Field-Dependent Mobility

In this paper, a physical model for a SiC Junction Field Effect Transistor (JFET) is presented. The novel feature of the model is that the mobility dependence on both temperature and electric field is taken into account. This is particularly important for high-current power devices where the maximum conduction current is limited by drift velocity saturation in the channel. The model equations are described in detail, emphasizing the differences introduced by the field-dependent mobility model. The model is then implemented in Pspice. Both static and dynamic simulation results are given. The results are validated with experimental results under static conditions and under resistive and inductive switching conditions.

Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances

Transient behavior in switching operation of junction field-effect transistors (JFETs) is affected by their intrinsic parasitic capacitances. This paper focuses on the switching operation of lateral-type and vertical-type SiC JFETs with considering the charge/discharge behavior of parasitic capacitances in the device. Their device structure decides the voltage dependency of the capacitance characteristics, so that the C-V characteristics governs their switching behavior.

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

AbstractThis paper reviews the normally‐off (N‐ off) and normally‐on (N‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures.Migration enhanced embedded epitaxy (ME3) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance (RON) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations.The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm2. N‐ off and N‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific RON of the N‐ off and N‐ on DGTJFETs is at room temperature 8.1 m Ω cm2 and 6.3 mΩ cm2, respectively, indicating that N‐ off devices can be realized at the expense of a slight increase in specific RON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 1015 cm–3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Extreme temperature 6H‐SiC JFET integrated circuit technology

AbstractExtreme temperature semiconductor integrated circuits (ICs) are being developed for use in the hot sections of aircraft engines and other harsh‐environment applications well above the 300 °C effective limit of silicon‐on‐insulator IC technology. This paper reviews progress by the NASA Glenn Research Center and Case Western Reserve University (CWRU) in the development of extreme temperature (up to 500 °C) integrated circuit technology based on epitaxial 6H‐SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs fabricated and packaged by NASA have now demonstrated thousands of hours of continuous 500 °C operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Design, modeling, and characterization of transistors and circuits at temperatures from 24 °C to 500 °C are also described. CWRU designs for improved extreme temperature SiC JFET differential amplifier circuits are demonstrated. Areas for further technology maturation, needed prior to beneficial system insertion, are discussed. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Substrate Bias Amplification of a SiC Junction Field Effect Transistor with a Catalytic Gate Electrode

The drain current-voltage (I-d-V-D) characteristics of a chemical gas sensor based on a catalytic metal insulator silicon carbide field effect transistor (SiC-FET) were measured in H-2 or O-2 ambient while applying negative substrate bias, V-sub, at temperatures up to 600degreesC. An increase in the negative V-sub gives rise to an increase of the drain voltage at a given drain current level, which can be used to adjust the device baseline. In addition, we found that the difference in drain voltage between H-2 and O-2 ambient at a given drain current level (the gas response to H-2) increases for an increased negative substrate bias. By modifying an equation for the drain current in a SIT (static induction transistor), the influence of substrate bias on the amplification factors, mu and eta, was estimated using the temperature dependence of the I-d-V-D characteristics. From this, the effect of substrate bias on the gas response to hydrogen was calculated. It was clarified that the increase in the gas response caused by the negative substrate bias is due to a substrate bias dependence of the amplification factor of the short channel device.