SiC FET Research Articles

10 kV, 87 mΩcm<sup>2</sup> Normally-Off 4H-SiC Vertical Junction Field-Effect Transistors

SiC JFET, compared with SiC MOSFET, is attractive for high power, high temperature applications because it is free of gate oxide reliability issues. Trenched-and-Implanted VJFET (TIVJFET) does not require epi-regrowth and is capable of high current density. In this work we demonstrate two trenched-and-implanted normally-off 4H-SiC vertical junction field-effect transistors (TI-VJFET), based on 120μm, 4.9×1014cm-3 and 100μm, 6×1014cm-3 drift layers. The corresponding devices showed blocking voltage (VB) of 11.1kV and specific on-resistance (RSP_ON) of 124m7cm2, and VB of 10kV and RSP_ON of 87m7cm2. A record-high value for VB 2/RSP_ON of 1149MW/cm2 was achieved for normally-off SiC FETs.

Elucidation of the intrinsic loss arising from switch output capacitance Coss in ultra-high-speed low-loss power converters

Attempts to drive down the switching losses of hard-switched unipolar devices by increasing gate drive current levels are ultimately limited by the device output capacitance, which thus represents an intrinsic loss. The paper presents an in-depth analysis of the charging and discharging of the output capacitance and the associated loss producing mechanisms. It is shown that energy is stored in the depletion layer of the device during turn-off and then dissipated as heat during the turn-on process. The instantaneous power dissipated in the device is thus different to the instantaneous power loss measured at the device terminals, although the total energy loss over one complete turn-off and turn-on cycle is still faithfully reproduced. An analytical approach to determining the intrinsic switching loss due to the output capacitance is presented and verified by experimental results and by TCAD simulation. It is shown that around 20% of the total switching losses arise from the intrinsic output capacitance loss under fast-switched inductive load conditions. A comparison of Si and SiC FET devices demonstrates the potential for SiC power devices to provide an energy efficient option for very high frequency switching.

SiC-DACFET

The nm-range abrupt doping profiles in SiC epitaxial layers are stable even after the high temperature process because SiC crystal exhibits little diffusion of impurities. Growth of the SiC delta-doped layers have been reported by our group and the others. We believe that the well-designed delta-doped epitaxial layers for the FET channels extend possibility of the power SiC FET. We proposed the SiC Delta-doped Accumulation Channel MOSFET (DACFET) consisting of the delta-doped layers for MOS channel and reported its high MOS-channel mobility. The vertical hot-wall-type CVD system was used to grow SiC epitaxial layers. The pulse valve, which supplied short (<ms) gas pulse flow, was directly connected to the CVD reactor to introduce the doping gases N 2. The pulse-doping technique enabled formation of the delta-doped-layer structure during SiC epitaxial growth. The n-type delta-doped layer as thin as 2 nm was fabricated with a peak N concentration of 1 × 10 19 cm −3. The electrical characteristics of the DACFET, for example threshold voltage and R on, can be tuned by controlling the delta-doped-layer structures in MOS channel. MOS-channel mobility of the normally-off lateral DACFET was measured to be >100 cm 2/V s. The vertical DACFET, whose blocking voltage was >600 V, was fabricated with the double-implantation MOS process. R on of the normally-off 2 μm-gate DACFET was measured to be 13 mΩ cm 2. Current density was observed to be >140 A cm −2 larger than Si-IGBT. Shortening of gate length and unit cell size of the SiC-DACFET using high-resolution lithography will result in R on <7 mΩ cm 2.

Electric characteristics of normally-off type 5 kV class 4H-SiC JFET, "SEJEET"

A normally-off type 5.3kV 4H-SiC JFET with low specific on-resistance, called SEJFET (Static Expansion channel JFET), has been fabricated. Its normally-off operation was realized by a thin regrown epitaxial channel layer and using the buried p+ regions as a gate in addition to the top p+ regions. The achieved blocking voltage is the highest class BV among the reported SiC JFET. In a 5.3kV 4H-SiC SEJFET, the lowest specific on resistance of 69mΩcm2. Furthermore, the highest current capability among SiC JFET of 3.3A is achieved. In all reported FETs, the SEJFET has the best trade-off between RonS and blocking voltage (BV), which is about 1/230th lower than theoretical limit of a Si FET. Furthermore, the figure of merit (BV2/RonS) is 407MW/cm2, and this value is the highest among reported normally off SiC FETs.

Demonstration of first 10 kV, 130 mΩ cm 2 normally-off 4H-SiC trenched-and-implanted vertical junction field-effect transistor

The first demonstration of a trenched-and-implanted normally-off 4H-SiC vertical junction field-effect transistor with a 120 µm, ∼4.9×1014 cm−3 doped drift layer is reported, resulting in a record high blocking voltage VB of 10 400 V and a specific on-resistance (RSP_ON) of 130 mΩ cm2, leading to the highest VB2/RSP_ON of 832 MW/cm2 reported to date for normally-off SiC FETs.

High-transconductance beta -SiC buried-gate JFETs

An improved performance buried-gate SiC junction field-effect transistor (JFET) has been fabricated and evaluated. This structure uses an n-type beta -SiC film epitaxially grown by chemical vapor deposition on the Si(0001) face of a p-type 6H alpha -SiC single crystal. The current in the n-type channel was modulated using the p-type alpha -SiC layer as a gate. Electron-beam-evaporated Ti/Au was utilized as an ohmic contact to the n-type beta -SiC layer, and thermally evaporated Al was used to contact the p-type gate. A maximum DC transconductance of 20 mS/mm was obtained, which is the highest reported for a beta -SiC FET structure. The experimental data are analyzed using a charge-control model. Calculated drain current versus drain voltage characteristics for a buried-gate JFET are in good agreement with experimental data. >