Si3N4 Dielectrics Research Articles

Gate dielectric material influence on DC behavior of MO(I)SHEMT devices operating up to 150 °C

In this work, the DC behavior of AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MO(I)SHEMTs) with two different gate dielectrics (Al2O3 and Si3N4) is analyzed through the experimental comparison of their basic and analog parameters. The transistors with Si3N4 insulator are more closely related to the normally-off devices (less negative threshold voltage) and less affected by the short channel effects (better DIBL behavior). Although the devices with Si3N4 layer presented a double conduction, that results in anomalous transconductance behavior, it is more suitable for analog applications since the Al2O3 devices suffer large self-heating. The very high gate leakage of Si3N4 MISHEMT degrades the subthreshold regime, which decreases the transistor efficiency at weak inversion. On the other hand, the devices with Si3N4 insulator present relatively large Early voltage and consequently high intrinsic voltage gain in strong inversion, reaching 84 V/V (38.5 dB). Even at high temperatures the intrinsic voltage gain is practically the same, degrading only 1.5 dB from 25 °C to 150 °C for a long channel device.

An improved methodology for extracting interface state density at Si3N4/GaN

In this Letter, a series of metal-insulator-semiconductor capacitors consisting of Si3N4 dielectrics with different thicknesses on GaN have been fabricated to investigate their interface states. The measurement value extracted from ultraviolet assisted capacitance-voltage methods can be explained by the existence of spatially uniform hole traps in Si3N4. An improved model combining the effects from interface states and hole traps in Si3N4 is proposed to extract the interface state density (Dit) accurately. Based on the model, Dit can be obtained by extrapolating the trap density to a zero-thickness dielectric. The extracted average Dit value of the Si3N4/GaN interface is ∼3.8 × 1011 cm−2 eV−1, and the hole trap concentration in Si3N4 is ∼3.1 × 1018 cm−3. The results, model, and analysis presented here provide new insights into studying Dit of various dielectrics on GaN and other wide-bandgap semiconductors.

Flatband voltage stability and time to failure of MOCVD-grown SiO2 and Si3N4 dielectrics on N-polar GaN

The flat-band voltage (VFB) stability and time-dependent-dielectric-breakdown of SiO2 and Si3N4 films grown in situ on (000–1) N-polar GaN by metal organic chemical vapor deposition are investigated. The VFB of the SiO2-film was unstable only above a critical electric-field stress of 4.3 MV cm−1, while the VFB of Si3N4 was unstable at both low and high electric fields. The Si3N4 film exhibited time to failure of 20 years occurring at an electric field of 4.9 MV cm−1 which was 3 MV cm−1 higher than that of SiO2. This study contributes to the understanding of dielectrics performance, devoted to next-generation N-polar GaN-based transistors.

Ion Beam Assisted E-Beam Deposited TiN Microelectrodes-Applied to Neuronal Cell Culture Medium Evaluation.

Microelectrode material and cell culture medium have significant roles in the signal-to-noise ratio and cell well-being in in vitro electrophysiological studies. Here, we report an ion beam assisted e-beam deposition (IBAD) based process as an alternative titanium nitride (TiN) deposition method for sputtering in the fabrication of state-of-the-art TiN microelectrode arrays (MEAs). The effects of evaporation and nitrogen flow rates were evaluated while developing the IBAD TiN deposition process. Moreover, the produced IBAD TiN microelectrodes were characterized by impedance, charge transfer capacity (CTC) and noise measurements for electrical properties, AFM and SEM for topological imaging, and EDS for material composition. The impedance (at 1 kHz) of brand new 30 μm IBAD TiN microelectrodes was found to be double but still below 100 kΩ compared with commercial reference MEAs with sputtered TiN microelectrodes of the same size. On the contrary, the noise level of IBAD TiN MEAs was lower compared with that of commercial sputtered TiN MEAs in equal conditions. In CTC IBAD TiN electrodes (3.3 mC/cm2) also outperformed the sputtered counterparts (2.0 mC/cm2). To verify the suitability of IBAD TiN microelectrodes for cell measurements, human pluripotent stem cell (hPSC)-derived neuronal networks were cultured on IBAD TiN MEAs and commercial sputtered TiN MEAs in two different media: neural differentiation medium (NDM) and BrainPhys (BPH). The effect of cell culture media to hPSC derived neuronal networks was evaluated to gain more stable and more active networks. Higher spontaneous activity levels were measured from the neuronal networks cultured in BPH compared with those in NDM in both MEA types. However, BPH caused more problems in cell survival in long-term cultures by inducing neuronal network retraction and clump formation after 1–2 weeks. In addition, BPH was found to corrode the Si3N4 insulator layer more than NDM medium. The developed IBAD TiN process gives MEA manufacturers more choices to choose which method to use to deposit TiN electrodes and the medium evaluation results remind that not only electrode material but also insulator layer and cell culturing medium have crucial role in successful long term MEA measurements.

Bipolar resistive switching in metal-insulator-semiconductor nanostructures based on silicon nitride and silicon oxide

Bipolar resistive switching in metal-insulator-semiconductor (MIS) capacitor-like structures with an inert Au top electrode and a Si3N4 insulator nanolayer (6 nm thick) has been observed. The effect of a highly doped n+-Si substrate and a SiO2 interlayer (2 nm) is revealed in the changes in the semiconductor space charge region and small-signal parameters of parallel and serial equivalent circuit models measured in the high- and low-resistive capacitor states, as well as under laser illumination. The increase in conductivity of the semiconductor capacitor plate significantly reduces the charging and discharging times of capacitor-like structures.

Finite Element Modelling To Evaluate the Cross-plane Thermal conductivity and Seebeck Coefficient of Ge/SiGe Heterostructure

Finite element modelling (FEM) is used to evaluate a new experimental procedure for extracting the thermal conductivity and Seebeck coefficients from micro-fabricated structures with integrated heaters, thermometers and Ohmic contacts. This experimental technique was designed to simultaneously produce and measure the differential temperature and voltage output for the determination of both thermoelectric properties of Ge/SiGeheterostructures.This study demonstrates the reliability of the FEM modelling by comparing the simulation results with experiment. It demonstrates how FEM can be implemented to complement the experiments: it can be used to observe the heat distribution in the heterostructure. Therefore all the mechanisms of parasitic heat loss in the devices can be evaluated in order to improve the accuracy of the extraction of thermal coefficients and especially the thermal conductivity. This will allow for further analysis to be taken to optimize the ZT and power factor for the Ge/SiGeheterostructures.The micro-fabricated structures consisted of an etched mesa of the Ge/SiGeheterostructure with Ohmic contacts, for measuring the voltages, at the top and bottom. On the top of the mesa, a 30nm thick Si3N4 insulator was applied followed by a Ti/Pt thermometer, another 70nm of Si3N4 and then a NiCr heater. A second thermometer was micro-fabricated at the bottom of the mesa to allow the ▵T across the material to be measured as a function of the heater power [1]. The results obtained from the FEM studies closely matches the experimental results in [1].

Electronic confinement in modulation doped quantum dots

Modulation doping, an effective way to dope quantum dots (QDs), modifies the confinement energy levels in the QDs. We present a self-consistent full multi-grid solver to analyze the effect of modulation doping on the confinement energy levels in large-area structures containing Si QDs in SiO2 and Si3N4 dielectrics. The confinement energy was found to be significantly lower when QDs were in close proximity to dopant ions in the dielectric. This effect was found to be smaller in Si3N4, while smaller QDs in SiO2 were highly susceptible to energy reduction. The energy reduction was found to follow a power law relationship with the QD size.

Dependence of the sizes of damaged regions around indium contacts to p-type CdHgTe on GaAs substrates on the annealing temperature and time

It is found that damaged regions are formed around indium contacts to p-type CdHgTe {310} heteroepitaxail layers (HELs) on GaAs substrates and the sizes of these regions depend on the temperature and time of annealing in air. It is shown experimentally that at an annealing temperature of 90 °C, the rate of expansion of the damaged regions is about 4 µm/h, and at temperatures of 120 °C, it is more than 25 µm/h. After 488 hours of annealing of plates of CdHgTe HELs at 60 °C in air, the formation of damaged regions around the indium contacts to the p regions was not observed. The studies were performed on plates of p-type CdHgTe HELs on GaAs substrates whose surface was covered with SiO2 and Si3N4 dielectrics (with a total thickness of about 0.15 µm), with windows where p-n junctions were generated by ion implantation of boron.

Electrical properties of MBE grown Si3N4–cubic GaN MIS structures

AbstractIn this work we report on the electrical characterization of non‐polar cubic GaN metal‐insulator‐semiconductor (MIS) structures. Si3N4 layers were deposited in‐situ on top of cubic GaN grown on 3C‐SiC (001) substrates. The electric characteristics of the MIS structures are measured by capacitance and admittance spectroscopy techniques. From the hysteresis in the capacitance‐voltage curves and the peak height of the conductance Gp –ω frequency curves the interface state densities are calculated.We find interface traps about 0.3 eV below the conduction band. The density of these traps is Dit = 2.5x1011 cm‐2eV‐1. This is one order of magnitude lower than in MIS structures with a Si3N4 insulator produced by plasma enhanced vapour deposition and two orders of magnitude lower than in MIS structures on c‐GaN with SiO2 as insulator (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Single-crystalline Ge nanowires and Cu3Ge/Ge nano-heterostructures

Single-crystalline germanium nanowires were synthesized via vapor–liquid–solid mechanism. The characteristics of the Ge nanowires were investigated by a transmission electron microscope to identify the [111] growth direction. The Ge nanowire-based field-effect-transistors on Si3N4 dielectrics were fabricated, showing a p-type semiconducting behavior with hole mobility of 47.03 cm2 V−1 s−1. The formation of Cu3Ge/Ge/Cu3Ge nanoheterostructures was demonstrated with the reaction between copper contacts and Ge nanowires by rapid thermal annealing. The diameter-dependent electrical transport property of Ge nanowires indicates that with diameters of more than 80 nm, the resistivity of Ge nanowires decreased with diameter decrease, while with diameters of less than 80 nm, it increased. With multiple annealing processes, the channel length of the Ge nanowire transistors can be successfully controlled. From electrical measurements of each annealing step, the electrical transport property was significantly improved by sequential formation of Cu3Ge contacts. The gradual formation of the germanide structure reduces Fermi level pinning effect and increases the Ohmic behavior of electrical transportation.

Growth and properties of single-crystalline Ge nanowires and germanide/Ge nano-heterostructures

Single-crystalline Ge nanowires have been synthesized on Au-coated Si substrates through a thermal evaporation, condensation method and vapor–liquid–solid mechanism. The [111] growth direction of the Ge nanowires was analyzed using HRTEM and fast Fourier transform diffraction patterns. Global back-gated Ge nanowire field-effect transistors (FETs) on the Si3N4 dielectrics were fabricated and studied, showing p-type behavior and a field effect hole mobility of 44.3 cm2 V−1 s−1. The Ge channel length could be well controlled through the annealing process. After a rapid thermal annealing (RTA) process, Ni2Ge/Ge/Ni2Ge nano-heterostructures were formed. The electrical transport properties were effectively improved by the heterojunction rather than the metal contact. The epitaxial relationship between Ge and orthorhombic Ni2Ge was Ge[110]//Ni2Ge[110] and Ge(-11-1)//Ni2Ge(1-1-2). From electrical transport properties, the measured resistivity of the Ge nanowires was much lower than intrinsic bulk Ge material. A room temperature photoluminescence spectrum of the Ge nanowires possessed a broad blue emission with a peak at 462 nm in wavelength, which was attributed to the oxide-related defect states. Due to the existence of the defects, a Ge nanowire FET was able to detect visible light and serve as a nanowire photodetector.

HfO2, Sr-Ta-O and Ti-Ta-O High-k Dielectrics for Metal-Insulator-Metal Applications

Atomic Vapor Deposition (AVD) technique was successfully applied for the depositions of amorphous HfO2, Sr-Ta-O and Ti-Ta-O thin films, which were investigated as alternative dielectrics to replace the standard SiO2 or Si3N4 dielectrics used in Metal-Insulator-Insulator (MIM) structures. Metal oxides were grown on 200 mm TiN/Si (100) substrates within the thermal budget of back-end-of-line (BEOL) process. Electrical properties, investigated after sputtering Au top electrodes, revealed that the main characteristics are different for each dielectric. On one hand, Ti-Ta-O based MIM capacitors possessed a dielectric constant of 50, which is more than a factor of 2 higher compared to the ones of Sr-Ta-O (20) and HfO2 (18). On the other hand, Sr-Ta-O based MIM capacitors showed the lowest leakage current densities as well as the smallest capacitance-voltage linearity coefficients. Values as large as 5.9 MV/cm for the breakdown strengths are obtained for the HfO2 based MIMs.

Alternative High-k Dielectrics for Metal-Insulator-Metal Applications

Atomic Vapor Deposition (AVD) technique was successfully applied for the depositions of amorphous HfO2, Sr-Ta-O and Ti-Ta-O thin films, which were investigated as alternative dielectrics to replace the standard SiO2 or Si3N4 dielectrics used in Metal-Insulator-Insulator (MIM) capacitors. Metal oxides were grown on 200 mm TiN/Si (100) substrates within the thermal budget of back-end-of-line (BEOL) process. Electrical properties, investigated after sputtering Au top electrodes, revealed that the main characteristics are different for each dielectric. On one hand, Ti-Ta-O based MIM capacitors possessed a dielectric constant of 50, which is more than a factor of 2 higher compared to the ones of Sr-Ta-O (20) and HfO2 (18). On the other hand, Sr-Ta-O based MIM capacitors showed the lowest leakage current densities as well as the smallest capacitance-voltage linearity coefficients.

Large resistive-switching phenomena observed in Ag/Si3N4/Al memory cells

An effective resistive-switching effect has been observed in silicon nitride (Si3N4) dielectrics in Ag/Si3N4/Al memory cells. The ratio of the low resistance to high resistance state was larger than 107 at ±1.2 V for a 10 nm thick Si3N4 layer. This switching behavior is attributed to a change in the conductivity of the Si3N4 dielectrics, depending on whether nitride-related traps are filled with electrons under positive biases or unfilled under negative biases. This assertion is experimentally confirmed from the relationship between the amount of charges trapped in the Si3N4 layer and the corresponding changes in its resistance with respect to bias voltages. In addition, the formation or dissolution of the conductive path is confirmed by conductive atomic force microscopy current images.

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with <formula formulatype="inline"><tex Notation="TeX">$\hbox{HfO}_{2}$</tex></formula> as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum <emphasis emphasistype="smcaps">on</emphasis>-state drain current is higher than 5.5 A. Performance of small devices with <formula formulatype="inline"><tex Notation="TeX">$\hbox{HfO}_{2}$ </tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$\hbox{Si}_{3}\hbox{N}_{4}$</tex></formula> dielectrics is compared. The electric strength of gate dielectrics is measured for both <formula formulatype="inline"><tex Notation="TeX">$ \hbox{HfO}_{2}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$\hbox{Si}_{3}\hbox{N}_{4}$</tex></formula>. Devices with <formula formulatype="inline"><tex Notation="TeX">$\hbox{HfO}_{2}$</tex></formula> show better uniformity and lower leakage current than <formula formulatype="inline"><tex Notation="TeX">$\hbox{Si}_{3}\hbox{N}_{4}$</tex></formula> passivated devices. The 5.5-A <formula formulatype="inline"><tex Notation="TeX">$\hbox{HfO}_{2}$</tex></formula> devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 <formula formulatype="inline"><tex Notation="TeX">$\Omega \cdot \hbox{mm}$</tex></formula> or 2.5 <formula formulatype="inline"> <tex Notation="TeX">$\hbox{m}\Omega\cdot \hbox{cm}^{2}$</tex></formula>). </para>

SONOS-Type Flash Memory Cell With Metal$/\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{SiN}/\hbox{Si}_{3}\hbox{N}_{4}/\hbox{Si}$ Structure for Low-Voltage High-Speed Program/Erase Operation

High-quality Al2O3 and Si3N4 dielectrics synthesized in a molecular/atomic deposition system were developed and adopted as blocking oxide and tunnel dielectric, respectively in a SONOS-type NAND flash memory cell. In particular, the use of trap-free Si3N4 as tunnel dielectric enables low-voltage erase operation due to its low barrier height for holes, and the relatively high-k value of Al2O3 enhances the low-voltage and high-speed program/erase (P/E) operations. We fabricated and investigated NAND flash memory cells with metal/Al2O3/SiN/Si3N4/Si structure. The fabricated cell shows 3.8-V memory window with P/E conditions of +15 V for 100 mus and -10 V for 10 ms. It also shows good endurance up to 10 000 cycles and more than 1.5-V memory window after ten years.

Photoresponse of the In 0.3 Ga 0.7 N metal–insulator–semiconductor photodetectors

In 0.3Ga 0.7N metal–insulator–semiconductor (MIS) and metal–semiconductor (MS) surface barrier photodetectors have been fabricated. The In0.3Ga0.7N epilayers were grown on sapphire by metalorganic chemical vapour deposition (MOCVD). The photoresponse and reverse current–voltage characteristics of the In0.3Ga0.7N MIS and MS photodetectors were measured. A best zero bias responsivity of 0.18 A/W at 450 nm is obtained for the In0.3Ga0.7N MIS photodetector with 10 nm Si3N4 insulator layer, which is more than ten times higher than the In0.3Ga0.7N MS pho-todetector. The reason is attributed to the decrease of the interface states and increase of surface barrier height by the inserted insulator. The influence of the thickness of the Si3N4 insulator layer on the photoresponsivity of the MIS photodetector is also discussed.

Process-Dependent Charges and Traps in Dielectrics on SiC

Dielectric charges and charge stability were compared in different dielectrics formed on SiC by different processing techniques. The concentration and transient behavior of the interface and trapped charges were investigated. Strong hysteresis and flat-band voltage drift under applied bias were observed in some of the samples. They are attributed to the trapping of the charge injected in the dielectrics. Differences in charge injection, charge trapping, and capture/emission of carriers by interface traps were pronounced for the investigated SiO2 and Si3N4 dielectrics.

Al2O3/Si3N4 Buffer Layer for High Performance MFIS (Metal-Ferroelectric-Insulator-Semiconductor) Transistors

AbstractThe Al2O3 thin films were deposited on the Si3N4 (radical- Si3N4) prepared by the direct nitridation of a Si substrate using atomic nitrogen radicals. Because the radical- Si3N4 is highly resistive against the oxidation process, we can completely eliminate the metal phase in Al2O3 that degrades the insulating properties of Al2O3. The 1.3nm thick Al2O3 film was found to have a permittivity of 9.76 in this stacked Al2O3/Si3N4 structure. It was also found that no oxidation took place at the interface of Si3N4 and the Si substrate during the deposition and post-oxidation of the Al2O3 film on the radical-Si3N4/Si substrates. As a result, highly capacitive MIS (Metal-Insulator-Semiconductor) structures were realized using the Al2O3/Si3N4 stacked insulator. The MIS diode with Al2O3/Si3N4 is found to have 105 times less leakage current compared to the diode with Si3N4 insulator film with similar capacitance density. We have shown that the insulating properties of the Al2O3/radical-Si3N4 stack are suitable for the MFIS (Metal-Ferroelectric-Insulator-Semiconductor) transistors.

Silicon‐insulator interface probing by reflected optical second harmonic generation

AbstractOptical second harmonic generation (SHG) has been applied to the study of the silicon–insulator (SI) interface. Results from real‐time measurements of the SHG intensity during etching process of SiO2 and Si3N4 insulator layers are presented and analysed taking into consideration various contributions to the nonlinear polarization in the SI interface such as the silicon substrate, the static electric field, the inhomogeneous deformation and the crystalline oxide interlayer. The symmetry properties of the silicon–insulator interface have also been determined by an analysis of the SHG rotational dependences.