Si ULSI Research Articles

Self-Assemble Formation of Ge Dots on Si(100) via C/Ge/C/Si Structure

Self-assemble formation of Ge quantum dots on Si is one of the promising candidates to implement optical devices, such as laser diodes [1], photo detectors [2] and solar cells [3], on a Si ULSI platform. It has been reported that the usage of sub-monolayer (ML) carbon (C) gave a beneficial way to form Ge dots as a result of c(4×4) reconstruction on Si(100) [4]. In our previous studies, self-assemble formations of Ge dots by C mediation were investigated as follow. In the case of sequential deposition of C and Ge on Si (Ge/C1/Si structure) at low temperature and subsequent annealing, it was confirmed that Si-C bonds promoted to form Ge dots during solid phase epitaxy [5]. In the case of C2/Ge/Si structure, an incorporation of C atoms into Ge layer during annealing induced to decrease the bulk free energy due to the formation of Ge-C bonds in the nucleation process, and led to scale down dot size and increase dot density [6]. On the basis of these backgrounds, by combining both structures, Ge dot formation via C2/Ge/C1/Si structure was investigated in this study. This is because the formation of Si-C bonds at the Ge/Si interface and Ge-C bonds in Ge dots is expected to help to obtain small and high-density Ge dots. The samples were prepared by solid-source molecular beam epitaxy system. C2/Ge(7.5 ML)/C1/Si(100) structures by changing C1 and C2 coverage were formed at substrate temperature of 200°C and were annealed at 650°C in the MBE chamber. As a result, small (20 nm) and dense (1.7 × 1010 cm-2) Ge dots were obtained at C1 = 0.25 ML and C2 = 0.1 ML. This indicates that the C2/Ge/C1/Si structure, which enables to control the binding states of both Si-C and Ge-C bonds, is an effective way to form Ge quantum dots self-assembly. In the meeting, the influence of the relationship between C1 and C2, the dot formation mechanism related to C binding states, and the optimization of the C2/Ge/C1/Si structure will be presented in detail. Acknowledgments This study was partially supported by JSPS KAKENHI Grant Number 24246003 and 15H03554 and, JSPS Core-to-Core Program, A. Advanced Research Networks. Reference [1] F. Ross et al., Phys. Rev. Lett. 80 (1998) 984. [2] G. Abstreiter et al., Semicond. Sci. Technol. 11 (1996) 1521. [3] A. Alguno et al., Appl. Phys. Lett. 83 (2003) 1258. [4] O. Leifeld et al., Mat. Sci. Eng. B 74 (2000) 222. [5] S. Hatakeyama et al., Microelec. Eng. 125 (2014) 28. [6] Y. Itoh et al., Materials Today Asia 2014 O2.2 (2014).

Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch

In this paper, we propose the novel Dynamic Feedback (DF-) MCML technique for high-speed and high-gain MCML type latch. The concept of the proposed DF-MCML technique is as follows; the output node signal is feedbacked to the input node in Sampling-Mode, and the output node is opened from the input node in Holding-Mode. It is shown by analytic theory that by this dynamic feedback sequence, both stability and sensibility of latch in Sampling-Mode is exponentially improved, and the gain of latch in Holding-Mode is drastically increased. Finally, we have numerically investigated the circuit performance of the novel DF-MCML type latch in comparison with the conventional MCML type latch by using P-Spice simulator. The maximum operation frequency of 180nm DF-MCML type latch reaches over 20GHz that is 2 times than the conventional MCML type latch. It is made clear that the proposed novel Dynamic Feedback MCML technique is suitable for over 10GHz high-speed and high-gain Si ULSIs.

Light emitting devices based on silicon nanostructures

In this paper, we summarize the results of an extensive investigation on the properties of MOS-type light emitting devices based on silicon nanostructures. The performances of crystalline, amorphous and Er-doped Si nanostructures are presented and compared. We show that all devices are extremely stable and robust, resulting in an intense room temperature electroluminescence (EL) at around 900 nm or at 1.54 μm. Amorphous nanostructures may constitute an interesting system for the monolithic integration of optical and electrical functions in Si ULSI technology. In fact, they exhibit an intense room temperature EL with the advantage to be formed at a temperature of only 900 °C, remarkably lower than the temperature needed for the formation of Si nanocrystals (1100 °C or higher). To improve the extraction of the light, we coupled the emitting system with a 2D photonic crystal structure properly fabricated with ULSI technology to reduce the total internal reflection of the emitted light. We demonstrate that the extraction efficiency is increased by a factor of 4. Finally, the light emission from devices based on Er-doped Si nanoclusters has been studied and in particular we have investigated the luminescence quenching processes limiting quantum efficiency in these devices. In fact the carrier injection, that determines the excitation of Er ions through electron–hole recombination, at the same time produces an efficient non-radiative Auger de-excitation with trapped carriers. These data are presented and the implications on the device performances discussed.

Electroluminescence and transport properties in amorphous silicon nanostructures

We report the results of a detailed study on the structural, electrical and optical propertiesof light emitting devices based on amorphous Si nanostructures. Amorphous nanostructuresmay constitute an interesting system for the monolithic integration of optical and electricalfunctions in Si ULSI technology. In fact, they exhibit an intense room temperatureelectroluminescence (EL), with the advantage of being formed at a temperature of900 °C, whileat least 1100 °C is needed for the formation of Si nanocrystals. Optical and electrical properties ofamorphous Si nanocluster devices have been studied in the temperature range between 30and 300 K. The EL is seen to have a bell-shaped trend as a function of temperature with amaximum at around 60 K. The efficiency of these devices is comparable to that found indevices based on Si nanocrystals, although amorphous nanostructures exhibit peculiarworking conditions (very high current densities and low applied voltages). Time resolvedEL measurements demonstrate the presence of a short lifetime, only partially due to theoccurrence of non-radiative phenomena, since the very small amorphous clusters formed at900 °C are characterized by a short radiative lifetime. By forcing a current through the device aphenomenon of charge trapping in the Si nanostructures has been observed. Trappedcharges affect luminescence through an Auger-type non-radiative recombination of excitons.Indeed, it is shown that unbalanced injection of carriers (electrons versus holes) isone of the main processes limiting luminescence efficiency. These data will bereported and the advantages and limitations of this approach will be discussed.

Low Temperature Preparation of Functional Oxide Thin Film by Sol-gel-Hydrothermal Process-Application to Si ULSI Monolithic Process for Large-Scale Integrated Sensor, Actuator, and Memory-

A very low-temperature process for preparation of functional oxide thin films is newly proposed and examined by sol-gel-hydrothermal combined treatment. A series of oxide ferroelectric thin films have been prepared by the method in various mineralizer, alkaline solutions. Especially PZT film grown in KOH+Pb(OH)2 solution at final post-baking temperature as low as 400°C, showed a well-saturated, good P-E hysteresis loop with Pr=26.3μC/cm2 and Ec=40.1 kV/cm, respectively.

Introduction in space technologies, processing and applications of ULSI/WSI/3D-WSI on functional 3D nano- and optoelectronic elements

Dynamics and reforms by which the semiconductor industry could be transformed into next-generation manufacturing of Si and nano-electronic ULSI and WSI are discussed. For competitive Si ULSI and WSI the functional integration becomes a core design principle and cardinal simplification of manufacturing processes/equipment becomes a core technology principle. Concept of single-wafer single-lithography (no-lithography on spacefabs) technology for nano-electronic complementary bipolar field-effect (CBFE), Vertical Merged MOS (VMMOS) and optoelectronic VMMOS (OVMMOS), CBFE (OCBFE) elements increasing the packaging density for high-speed low-voltage ULSI and WSI is considered. Technology and Economics (Technonomics) concepts of space hyperhigh-vacuum technologies and processing in framework of flexible scalable no-lithography spacefab under condition of low and high orbital flight are presented.

Nanofabrication toward sub-10 nm and its application to novel nanodevices

The device feature size in Si ULSIs has been reduced over the years, and sooner or later we will probably enter the so-called nanoelectronics era. Two nanofabrication technologies, electron-beam lithography and atomic-beam holography, which are expected to play an important role in the coming era, are discussed first. In order to get finer patterns with electron-beam lithography, improvements in the characteristics of organic resists are crucially important. Organic negative resists with a fine resolution have been developed, and a high-quality resist line pattern with a width as small as 7 nm has been successfully formed. A new atom manipulation technique called atomic-beam holography has been proposed for nanofabrication. It enables direct pattern formation on a substrate by passing laser-cooled atoms through a computer-generated hologram. It is expected to be a technique with a fine resolution, reaching the atomic scale, and a high throughput. Nano-size devices are developed from two standpoints. One pursues the miniaturization limit of MOS transistors: in this context, we discuss the fabrication of MOS transistors with gate length down to 14 nm and their electrical characteristics. The other approach is to explore `breakthrough devices' that utilize quantum effects: single electron devices are one type of such devices. We discuss the operation of an all-metallic single-electron memory cell along with the electrical characteristics of a single-electron transistor made of aluminium.

Silicon single-electron tunnelling device interfaced with a CMOS inverter

A silicon single-electron tunnelling (SET) device with an oxidation-controlled narrow channel was fabricated on a silicon-on-insulator substrate. Measurements at liquid helium temperature show the clear Coulomb blockade effects. The Coulomb oscillations of the SET device are successfully transformed to voltage oscillations by combining it with an nMOSFET load. In addition, it is demonstrated that the obtained small voltage signals are amplified with a CMOS inverter operating at room temperature. These results constitute an important step toward the future hybrid Si ULSIs of SET and CMOS devices.

Suspended SOI structure for advanced 0.1-μm CMOS RF devices

Modern silicon-on-insulator (SOI) technology and 0.1-/spl mu/m-channel-length complementary metal oxide silicon (CMOS) devices make it possible to fabricate high-performance RF devices by using standard Si ULSI processes. Using the buried oxide layer of an SOI wafer as an etching stopper, we were able to integrate a suspended inductor, with high-inductor resonance-frequency of 19.6 GHz, and high-performance 0.1-/spl mu/m CMOS devices. Moreover, we experimentally show that this suspended CMOS has acceptable short-channel immunity. Using two-dimensional (2-D) simulation, we clarify that the gate-potential spread sufficiently suppresses the potential shifts, which results in good short-channel characteristics.

Structural and electrical characterization of epitaxial CdF2 layers grown on Si(111) and CaF2(111) substrates

The wide band-gap, group-II fluoride CdF2 exhibits semiconducting properties when doped with some rare earth impurities and annealed under appropriate conditions. In addition, CdF2 is closely lattice matched to Si and epitaxial layers of CdF2 on Si are of potential interest for integration of optoelectronic devices (such as light emitting diodes) with Si ULSI technology. In this work, approximately 300 nm-thick CdF2 films were grown on both Si and CaF2 substrates by molecular beam epitaxy (MBE). Characterizations of the films by reflection high energy electron diffraction (RHEED), X-ray diffraction (XRD), Rutherford back-scattering (RBS) and atomic force microscopy (AFM) allowed the growth conditions to be optimized. After growth, the structures were annealed in Cd vapor and their resistivity was measured by a simple two-probe technique both before and after annealing. After annealing in Cd vapor at 500°C for 1 min, the resistivity of CdF2 films grown at 200°C on CaF2 substrates dropped below 0.1 Ω · cm from an as-grown value of 106 Ω · cm. On the other hand, films grown at 400°C had an as-grown resistivity of about 10 Ω · cm but did not decrease with annealing.

Application of nitrogen implantation to ULSI

Nitrogen is not a commonly used ion species in Si ULSI. It cannot be used as an n-type dopant because of its low solubility in Si. However, it shows interesting properties such as the suppression of boron diffusion when applied to source/drain doping and the nitridation of gate oxide when applied to gate doping. In this report, first, the effects of nitrogen preimplantation to the formation of boron-doped shallow p +n junctions are described. The technique is successfully applied to 0.25 μm PMOSFETs, forming shallow junctions and thus suppressing short channel effects. Next, the effects of nitrogen implantation into p + poly-Si gates are studied. The implanted nitrogen diffuses to the gate oxide during annealing and nitrides the gate oxide. As a result, boron penetration through the gate oxide is suppressed and the reliability and hot carrier resistance are improved.

Negative differential conductance in three-terminal silicon tunneling device

Negative differential conductance based on lateral band-to-band tunneling is demonstrated in a three-terminal silicon tunneling device. The device is fabricated with the current silicon ultra-large scale integration (Si ULSI) process, taking care of the field isolation to reduce the excess tunneling current that flows over some intermediate states. It is observed that the forward biased band-to-band tunneling current is largely controlled by the gate bias which modulates the tunneling barrier width. The three-terminal Si tunneling device is promising as the post complementary metal–oxide-semiconductor device in future Si ULSI.

Precursor design and selective aluminum CVD

Area-selective AI CVD technology has an excellent potential for filling via and contact holes of multilevel interconnection in Si ULSI. In this article, we discuss the selective AI CVD using metalorganic sources of trimethylaluminum [(CH 3) 3AI, TMA] and dimethylaluminum hydride [(CH 3) 2AIH, DMAH]. In order to deposit AI from TMA, the TMA molecule should be selectively excited into a reactive species of (CH 3) 2AI in the well controlled H 2/rf plasma. When using DMAH and H 2, AI can be deposited by low-pressure CVD; the features are (1) single crystal AI on Si surface, (2) filling capability into 0.3 μmΦ/1 μm-deep contact holes, (3) low contact resistivity (2 × 10 −7Ωcm 2) to n + − Si, and (4) erosion free at the Al/Si interface after 450 °C/30 min annealing. As a selective AI growth mechanism on the Si surface, we have proposed and experimentally confirmed a “surface electrochemical reaction model”. In this model, terminated-H on the Si surface reacts with CH 3-radical of the DMAH molecule to produce volatile CH 4. The H atom of the DMAH remains on the newly deposited AI surface as a newly terminated-H atom. The terminated-H atom on the surface reacts repeatedly with CH 3-radical to deposit AI. It is noted that, in the DMAH molecule, two CH 3-radicals and one H atom are bonded to AI atom, i.e. “asymmetric” structure. Since the different radicals are bonded to the AI atom, AI can be selectively and repeatedly deposited on Si surface. The precursor which has “asymmetric” structure is considered to have an important role for selective growth.

Future Ultra-Large Scale Integration: Transport Physics in Semiconductor Nanostructures

The progress in Si ULSI, and the parallel progress in GaAs LSI, has pushed the gate length in current devices toward 0.1 µm. Research laboratories have gone even further, and FETs with gate lengths as short as 20 nm have heen demonstrated. It is apparent that within the next decade or so, devices with gate lengths approaching this scale will be made in the production environment. These devices are likely to be susceptible to new physical effects that are now being studied in nanostructures, or mesoscopic devices as they are usually called. The first new effect, already seen in the short-gate length devices, is tunneling through the gate depletion region. In this paper, we try to summarize the major physical effects, some approaches to studying them, and the role they may play in future industrial devices.

Ecr Plasma Enhanced MOCVD of Titanium Nitride

AbstractThe ability to deposit high purity TiN by a CVD process that can provide improved conformality over current sputter deposition processes is critical for multilevel Si ULSI device applications. Low temperature deposition of high quality TiN films has been achieved by an ECR plasma enhanced CVD process using the metal-organic precursor, tetrakis(dimethylamido) titanium, Ti(N(CH3)2)4 (TDMAT). TDMAT is introduced into the downstream region of either a N2 or NH3 ECR plasma to deposit highly conducting films at deposition temperatures of as low as 100°C. The electrical resistivity of the TiN films decreases from 100-150μΩ-cm at a deposition temperature of 100°C to 45μΩ-cm at 600°C. The choice of plasma gas, N2 or NH3, affects the composition as well as the crystallographic texture of the films, which exhibit preferred (200) and (111) orientations, respectively. Pretreatment of the Si substrate with N2 or NH3 plasmas also affects the film morphologies, as demonstrated by switching the plasma gas between pretreatment and deposition.

In Situ Low Temperature Cleaning and Passivation of Silicon by Remote Hydrogen Plasma for Silicon-Based Epitaxy

ABSTRACTRemote Plasma-enhanced Chemical Vapor Deposition (RPCVD), which involves nonthermal, remote plasma excitation of precursors, has been demonstrated to be a novel and attractive technique for low temperature (150-450C) Si and Sil-xGex epitaxy for applications in Si ULSI and novel Si heterostructure devices which require compact doping profiles and/or heterointerfaces. An in situ low temperature remote hydrogen plasma clean in the Ultra-High Vacuum (UHV) deposition chamber in order to achieve a chemically passive, hydrogenated Si surface with minimal O, C and N contamination, is a critical component of the process. The ex situ wet chemical cleaning consists of ultrasonic degreasing and a modified RCA clean, followed by a final dilute HF dip. The in situ clean is achieved by remote plasma excited H, where H introduced through the plasma column is r-f excited such that the plasma glow does not engulf the wafer. In situ AES analysis shows that the remote H plasma clean results in very substantial reduction of the C, O and N contamination on the Si surface. We believe that the H plasma produces atomic H which, in turn, produces a reducing environment and has a slight etching effect on Si and SiO2 by converting them to volatile byproducts. TEM analysis of the wafers subjected to this clean indicate that defect-free surfaces with dislocation loop densities below TEM detection limits of 105 /cm2 are achievable. Corroborating evidence of achieving an atomically clean, smooth Si surface by remote H plasma clean as obtained from in situ RHEED analysis will also be presented. After in situ H cleaning at low pressures (45 mTorr), typically for 30 min. at a substrate temperature of 310 C, we observe both stronger integral order streaks compared to the as-loaded sample and the appearance of less intense half-order lines indicative of a (2 × 1) reconstruction pattern, indicating a monohydride termination. A (3 × 1) reconstruction pattern is observed upon H plasma clean at lower temperatures (250 C), which can be attributed to an alternating monohydride and dihydride termination. Results of air exposure of hydrogenated Si surfaces by AES analysis indicate that the (3 × l) termination is chemically more inert towards readsorption of C and 0. Successful Si homoepitaxy and Si/Sil-xGex heteroepitaxy under a variety of surface cleaning conditions prove that by a combination of these cleaning techniques, and by exploiting the inertness of the H-passivated Si surface, very low defect density films with 0 and C levels as low as 1X1018 cm−3 and 5×1017 cm−3, respectively, can be achieved.

Si ULSI : Will It Reach Its Limits?

Si ULSI : Will It Reach Its Limits?