Si Metal Oxide Semiconductor Structures Research Articles

Quantifying Flat-Band Voltage in Si Metal-Oxide-Semiconductor Structures: An Evaluation via Terahertz Emission Spectroscopy (TES)

Laser-induced Terahertz (THz) Emission Spectroscopy (TES) has demonstrated its potential utility in the realm of Metal-Oxide-Semiconductor (MOS) devices as an expedient and noncontact estimation methodology. Owing to its discerning response to the interface electric field, the amplitude of the THz emission peak in time-domain spectroscopy encapsulates rich information regarding MOS properties, notably the flat-band voltage. This paper concentrates on the precise quantitative estimation of the flat-band voltage within the Si MOS structure, elucidating the intricacies of the estimation process through the THz emission model.

Temperature-dependent analysis of charge carrier current in Al/SiO2/p-type Si MOS structures with TiN-induced traps via the Poole-Frenkel conduction mechanism using the vertical optimization method

In this study, we examined the Al/SiO2/p-type Si metal/oxide/semiconductor (MOS) structure across a temperature range of 303–423 K. To create intentional traps in the oxide, a 20 nm TiN layer was deposited. We analyzed the charge carrier current as a function of temperature using the Poole-Frenkel (PF) current mechanism and simultaneously extracted the five parameters (φ, Nh/e, µ, εr, and Vcorr) characterizing the PF current conduction process through the vertical optimization method (VOM), without the need for capacitance-voltage measurements or additional graphical methods. The barrier φ decreased with increasing temperature in both accumulation and inversion modes, with slopes of dφ/dT =−1.16 meV/K and−0.833 meV/K and intercepts of 3.07 eV and 3.45 eV, respectively. Carrier densities (Nh, Ne) also decreased as temperature rose, ranging from 7×1018–5×1010 cm−3 in accumulation mode and 6.5×1018–7.98×1016 cm−3 in inversion mode, indicating a more pronounced PF current mechanism in accumulation mode. Hole mobility (µh) remained significant up to 363 K but decreased sharply at higher temperatures, whereas electron mobility (µe) remained higher. The relative permittivity εr decreased with increasing temperature, indicating greater SiO2 polarization at lower temperatures. The voltage correction Vcorr varied with temperature, decreasing in accumulation mode by 1 Vcorr−acc = −1.33 V and increasing in inversion mode by 1 Vcorr−inv = 1.03 V. The oxide voltage correction at T = 0 K was found to be 2.606 V for holes (in accumulation) and −2.302 V for electrons (in inversion). The study concludes that trapping and detrapping mechanisms are more significant for holes in accumulation mode than for electrons in inversion mode. Consequently, the p-type MOS with PF leakage current is unsuitable for technological applications, while the n-type MOS shows promise, even at elevated temperatures, due to the less pronounced PF current mechanism.

Understanding terahertz emission properties from a metal–insulator–semiconductor structure upon femtosecond laser illumination

Metal–insulator–semiconductor (MIS) is an essential structure in semiconductor devices. Owing to the increasingly complex development of semiconductor devices, the local information of MIS, such as passivation, defects, and transient carrier dynamics, is becoming more challenging to characterize. Laser-excited terahertz (THz) emission spectroscopy and imaging are promising for investigating such local properties in a noncontact and nondestructive manner; however, the discussions are speculative and phenomenological. In this study, we formulate the mechanism of THz radiation based on a Si metal–oxide–semiconductor (MOS) structure to semi-quantitatively evaluate the MOS devices. A simplified model for both n- and p-type Si MOS structures is derived from Poisson's equation, which can effectively explain the dependence of THz emission amplitudes on external bias voltages considering external effects, including the flatband voltage, hot carrier diffusion, and quick recombination through interface states in addition to the photocurrent due to photocarrier field acceleration. The result reveals that one can estimate various “local” parameters such as the surface potential, semiconductor doping level, and dielectric constant of the passivation layer. The simplified model fills the gap between theory and observation, resulting in an advanced analytical tool for semiconductor research and development.

Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance–voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

Simulation of the influence of interface states on capacitance characteristics of insulator/AlGaN/GaN heterojunctions

We have studied numerically the capacitance properties of insulator/AlGaN/GaN MIS heterostructures and the influence of interface traps on the capacitance curves shape. By using the basic semiconductor equations we simulated the capacitance–voltage (C–V) curves of these structures for high-frequency signals. We obtained two steps in the C–V curves. The curves with the interface traps are shifted in voltage at both steps depending on whether the trap is of an acceptor or a donor type. The new knowledge found is that the shift caused by the change of the population of interface states is overlapped in almost the whole semiconductor energy gap by a charge change in a two-dimensional electron gas (2DEG). Finally, the presence of deep levels causes widening of the capacitance plateau instead of stretching of the C–V curves. So, the assessment of interface states density for MIS heterostructures is not expected to be so straightforward like in Si metal oxide semiconductor structures.

Effects of La2O3 Capping Layers Prepared by Different ALD Lanthanum Precursors on Flatband Voltage Tuning and EOT Scaling in TiN/HfO2/SiO2/Si MOS Structures

The use of thin capping layers that are inserted between the gate metal and dielectric layers have been shown to simultaneously cause a negative flatband voltage (Vfb) shift and to stabilize low threshold voltage (VTH). A major challenge with capping layers is to achieve adequate effective work function shifts without large increases in equivalent oxide thickness (EOT) (ΔEOT). In this work, the effects of La2O3 cap layers prepared by different ALD Lanthanum precursors, La(fAMD)3 and La(thd)3, on flatband voltage tuning and EOT scaling in TiN/HfO2/SiO2/Si metal oxide semiconductor (MOS) structures was investigated. Experimental results showed that ΔVfb and ΔEOT as high as 0.45 V and 0.055 nm, caused by dipoles at the lower interface between HfO2 and SiO2 interlayer and the diffusion of La and Hf atoms to the SiO2 interlayer, were achieved by a 1 nm thick La2O3 capping layer using a La(fAMD)3 precursor, while a relatively smaller Vfb and EOT of −0.7 V and 1.27 nm were obtained from the noncap TiN/HfO2/SiO2/Si MOSCAP sample. The use of a La(fAMD)3 precursor for the La2O3 capping layer deposition has been shown being much superior to La(thd)3 due to lower atomic layer deposition (ALD) process temperature and shorter O3 oxidant pulse duration.

Lateral photovoltaic effect and magnetoresistance observed in Co–SiO2–Si metal–oxide–semiconductor structures

We present an investigation on the magnetoresistance (MR) properties and lateral photoeffect (LPE) of thin Co films deposited on Si substrates with a thin native oxide layer. A marked transition on the transport properties of our films was observed around 250 K. The thinnest Co film exhibits the largest MR of 17.5%. We explain the transport and magnetotransport properties by the conducting channel switching from the upper metallic film to the Si inversion layer. Besides the MR, a large lateral photovoltage which depends in a linear way on the incident light spot position measured on the metallic film was also investigated. The largest open-circuit position sensitivity is 27.6 mV mm−1. The LPE was discussed in terms of metal–semiconductor junction.

Influence of interface layer composition on the electrical properties of epitaxial Gd2O3 thin films for high-K application

The authors report on the impact of interface layer composition on electrical properties of epitaxial Gd2O3 thin films on Si(001) substrates. The electrical properties of epitaxial Gd2O3 thin films were improved significantly by controlled modification of interface layer composition. The minimum capacitance equivalent thickness estimated for Pt∕Gd2O3∕Si metal oxide semiconductor structures was as low as 0.76nm with leakage current density of 15mA∕cm2 at (Vg−VFB)=1V. The corresponding density of interface states was found to be 2.3×1012cm−2eV−1. The authors also find that a change in the interface layer composition significantly alters band alignment of Gd2O3 layer with respect to Si substrates.

Efficient ultraviolet electroluminescence from a Gd-implanted silicon metal–oxide–semiconductor device

Strong ultraviolet electroluminescence with an external quantum efficiency above 1% is observed from an indium-tin oxide/SiO2:Gd∕Si metal–oxide–semiconductor structure. The SiO2:Gd active layer is prepared by thermal oxidation followed by Gd+ implantation and annealing. The electroluminescence spectra show a sharp peak at 316nm from the P7∕26 to S7∕28 transition of Gd3+ ions. Micrometer-sized electroluminescent devices are demonstrated.

InP and Si metal-oxide semiconductor structures fabricated using oxygen plasma assisted wafer bonding

In this paper, InP metal-oxide-semiconductor (MOS) structures are fabricated by transferring thermally grown SiO2 to InP from oxidized Si wafers using oxygen plasma assisted wafer bonding followed by annealing at either 125°C or at 400°C. Well-defined accumulation and inversion regions in recorded capacitance-voltage (C-V) curves were obtained. The long-term stability was comparable to what has been previously reported. The structures exhibited high breakdown fields, equivalent to thermally grown SiO2-Si MOS structures. The transferring process was also used to fabricate bonded Si MOS structures.

Determining Generation–Recombination Characteristics of a Semiconductor–Dielectric Interface from the Current Kinetics of Surface Minority Carrier Generation

Conditions for the one-to-one characterization of the generation (Gs) and surface recombination (Rs) rates of minority charge carriers (MCCs) in a metal–oxide–semiconductor (MOS) structure (in the case of strong nonequilibrium depletion) by the MCC surface generation current (I(t)) flowing in an external circuit of this structure are revealed. These conditions are the following: (1) the generation current I is independent of the time t (until the structure enters an equilibrium state) and the voltage Vg0 corresponding to the initial nonequilibrium depletion and (2) the duration of current steps I(Vg0) = const and, consequently, the equilibrium surface charge increase with increasing Vg0. The observed kinetics of the MCC generation current for the MCCs induced in an n-Si MOS structure at 293 K experimentally confirms the realization of these conditions. The values of the generation and recombination rates Gs = 2.84 × 1010 cm–2s–1 and Rs = 6.82 cm s–1 obtained from current levels I(Vg0) = const are typical of high-quality Si MOS structure. Additionally measured capacitance–voltage characteristics were used to determine the interface state density at the Si/SiO2 contact near the middle of the Si gap (Nss(E) ≅ 6.4 × 1010 cm–2eV–1), which allowed the estimation of the effective capture cross section of these states σ eff ≅ 1.4 × 10–16 cm2.

Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO2/Si metal–oxide–semiconductor structures

We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO2/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.

Observation of Oxide-Thickness-Dependent Interface Roughness in Si MOS Structure

The relationship between roughness at the Si/SiO2 interface and the oxide thickness was investigated by means of a nondestructive measuring method, using the Si metal-oxide-semiconductor (MOS) structure. It was demonstrated that the Si/SiO2 interface roughness recovers during thermal oxidation. This recovery process was also verified by observation with the transmission electron microscope (TEM). It was found that the recovery effect on the roughness at the Si/SiO2 interface depends on the oxidation process and that it is more significant in wet oxidation than in dry oxidation.

Thermal behavior of deep levels correlated with iron in silicon metal-oxide-semiconductor structure

Thermal behavior of deep levels correlated with iron in Si MOS (metal-oxide-semiconductor) structure has been studied by isothermal capacitance transient spectroscopy. As a result, it is shown that interstitial iron scarcely affects the interface trap (Nt) of MOS structure. This is made clear by measuring Nt of Si MOS diodes containing iron impurity, the interstitial component of which is controlled by low temperature annealings. In addition, the low temperature (400 °C) annealing decreases interstitial iron concentration as well as interface trap density. This phenomenon is very lucky for Si MOS devices.

Compositional and electrical properties of Si metal–oxide–semiconductor structure prepared by direct photoenhanced chemical vapor deposition using a deuterium lamp

High quality SiO2 layers have been grown on (111) Si substrates by direct photoenhanced chemical vapor deposition using monosilane (SiH4) and oxygen (O2) as gas sources under irradiation of a deuterium lamp. The refractive index of the deposited oxide is 1.462 at 250 °C when the gas ratio (O2/SiH4) is 5. The measurements of the Fourier transform infrared spectrum, x-ray photoelectron spectroscopy, and Auger electron spectroscopy show that the dominant components of the oxide are silicon and oxygen and the film is SiO2. Hysteresis free capacitance–voltage characteristics of the metal–oxide–semiconductor diode was observed. After low temperature postoxidation annealing, the minimum interface trap density is 1.5×1011 cm−2 eV−1, which is comparable to that of thermal oxidation.

Effects of gamma-ray irradiation on cubic silicon carbide metal-oxide-semiconductor structure

Radiation effects on cubic silicon carbide (3C-SiC) metal-oxide-semiconductor (MOS) structures have been studied with high-frequency capacitance-voltage measurements. It was <m1;38p>found that interface traps are generated at the 3C-SiC/SiO2 interface and oxide-trapped charges are built up in the oxide by 60Co gamma-ray irradiation. The generation of the interface traps and the oxide-trapped charges are affected by bias polarity applied to the gate electrode during the irradiation. Absorbed dose dependencies of their generation are discussed comparing with those of Si MOS structures.

Electrical properties of β-SiC metal-oxide-semiconductor structures

Using conductance and capacitance data for metal-oxide-semiconductor (MOS) structures on n-type β-SiC, the density of states at the β-SiC/SiO2 interface, their location in the bandgap of β-SiC, and the electron capture probability are obtained. The MOS structures were fabricated by oxidizing β-SiC in wet oxygen. It is found that interface-state density of the order of 1011 states/(cm2-eV) is located between 0.28–0.40 eV below the conduction-band edge of β-SiC. The electron-capture probability is in the range from 4.2×10−9 to 8.4×10−8 cm3/s. This study shows that the electrical properties of β-SiC MOS structures are similar to that of Si MOS structures.

Evidence for the occurrence of subcutaneous oxidation during low temperature remote plasma enhanced deposition of silicon dioxide films

Chemical vapor deposition of SiO2 is often thought of as an innocuous process by which an insulating layer can be formed without affecting the underlying substrate. Here evidence is presented which indicates that a subcutaneous oxidation process takes place during remote plasma enhanced chemical vapor deposition of SiO2 which oxidizes a few monolayers of the underlying substrate. This oxidation process is evidenced most directly by electrical measurements on metal–insulator semiconductor (MIS) structures fabricated on Ge and GaAs materials. These MIS structures utilize a thin Si interlayer between the semiconductor and the SiO2 to form relatively low interface state density structures. Electrical measurements indicate that depositing SiO2 60 nm in thickness results in consumption of the 1 to 2 nm Si layer through oxidation. The performance of Si metal–oxide semiconductor structures fabricated using deposited oxides degrades as the thickness of the oxide is increased. The presence of a poor quality, highly strained, subcutaneous oxide formed at low temperature could lead to degraded device performance. Work has been carried out in a separate set of experiments to characterize the nature of oxides formed by direct exposure of Si, Ge, GaAs, and CdTe to remote plasma excited oxygen species.

Summary Abstract: Experimental study of interfacial Na+ ‘‘impurities’’ in Si metal–oxide-semiconductor structures

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The Si–SiO2 interface: Correlation of atomic structure and electrical properties

The roughness at the Si–SiO2 interface has been determined quantitatively on an atomic scale by SPA-LEED (spot profile analysis of low energy electron diffraction) in ultrahigh vacuum after removal of the oxide. At the Si–SiO2 interface the steps are randomly distributed. With the help of model calculations the measured spot broadening provides the step atom density and therefore the roughness on an atomic scale. The roughness will be decreased by low oxidation rates (thick oxides, dry atmosphere) and appropriate annealing in N2 and will be increased by high oxidation rates (thin oxides and wet atmosphere). Furthermore metal oxide semiconductor (MOS) structures were built on chips which were also suited for LEED measurements. Hall mobilities for Si(111) p-channel inversion layers MOS-FETs with varying roughness at the Si–SiO2 interface have been measured at temperatures between 4.2 K and room temperature. It was found that there exists a strong correlation between Hall mobility and atomic roughness at high inversion, nearly a proportionality. Even at room temperature the transistors with the lower interface roughness exhibit the higher mobility. Further quasistatic capacitance–voltage (C–V) measurements have been performed on Si(111) MOS structures with different but well-known atomic roughness. The results demonstrate a strong correlation between atomic roughness and interface state density too, even after an additional postmetallization-annealing (PMA) treatment. A simple model which is associated with each kind of step atom, i.e., edge or kink atoms, suggests the creation of a dangling bond and therefore, a surface state can explain the result. Assuming that ionized atoms which are responsible for Qfix are located preferentially at those steps or kinks which are also correlated to the dangling bonds at the interface, we confirm the general opinion that Qfix and surface states have at least one common physical origin: the atomic roughness.