Si Metal Oxide Semiconductor Field Effect Research Articles

Low-Frequency Noise Assessment of Vertically Stacked Si n-Channel Nanosheet FETs With Different Metal Gates

This article presents a comparative low-frequency noise (LFN) characterization of gate-all-around nanosheet n-channel Si metal–oxide–semiconductor field effect transistors, processed with three different metal gates (MGs): an aluminum-based reference process and two alternative effective work function (EWF) stacks. In all cases, the gate dielectric is composed of HfO2 over an SiO2 interfacial layer. The LFN figures of merit are extracted, such as the oxide trap density and Coulomb scattering coefficient, and the correlations with the threshold voltage and the electron mobility are investigated. Carrier number fluctuations are confirmed as the dominant mechanism of the 1/ ${f}$ noise for all evaluated devices. Additionally, it is shown that the specific MG can contribute to the carrier scattering, degrading the electron mobility. The most promising results are obtained for one of the alternative MGs, exhibiting a low oxide trap density level, a low threshold voltage and insignificant mobility degradation.

Imaging of potential gradient on platinum induced by hydrogen adsorption

The local gradient of electrostatic potential in the Pt gate of a Si-metal oxide semiconductor field effect transistor has been visualized using a phase reconstruction method with through-focus images of transmission electron microscopy based on the transport-of-intensity equation, which was quantitatively corrected by electron holography. The potential change by hydrogen adsorption in a specimen was detected by taking the difference between H2-adsorbed and H2-not-adsorbed phase images. We found that the potential gradient was localized at Pt interfaces and that the direction of the polarization was Pt inward. The direct visualization suggests that the potential gradient originated from hydrogen dipoles generated and located at the Pt interfaces.

Device Analysis of Pt/Ti Gate Si-Metal–Oxide–Semiconductor Field-Effect Transistor Hydrogen Gas Sensors: Unintentional Oxygen Invasion into Ti Layers

Device Analysis of Pt/Ti Gate Si-Metal–Oxide–Semiconductor Field-Effect Transistor Hydrogen Gas Sensors: Unintentional Oxygen Invasion into Ti Layers

Device Analysis of Pt/Ti Gate Si-Metal–Oxide–Semiconductor Field-Effect Transistor Hydrogen Gas Sensors: Unintentional Oxygen Invasion into Ti Layers

We have investigated Pt/Ti-gate Si-metal–oxide–semiconductor field-effect transistors (MOSFETs) from the viewpoints of hydrogen gas sensors and also mother devices of Pt–Ti–O-gate Si-metal–insulator–semiconductor field-effect transistor (MISFET) hydrogen gas sensors. The Pt/Ti-gate Si-MOSFETs with uniform coverage of Ti layers over the gate area do not respond to hydrogen gases in general. The observed large variations of threshold voltage Vth and sensing amplitude ΔVg for the as-processed Pt (15 nm)/Ti (5 nm)-gate Si-MOSFETs originate from the initial unintentional oxygen invasion into the Ti layers at the beginning of phosphorus-doped silicon glass deposition. The air-annealed and succeeding hydrogen post-annealing procedure for Pt (15 nm)/Ti (5 nm)-gate Si-MOSFET hydrogen gas sensors recovers the uniformity of Vth distributions close to that of as-processed Pt (90 nm)/Ti (5 nm)-gate Si-MOSFETs and leads to a large sensing amplitude ΔVg. We have found a critical Vth, Vthc, at which the response to hydrogen gas exposure begins. We have introduced a percolation model in which the ratio of Ti contact area to the effective Pt contact area over the gate oxides will be reduced to zero in accordance with the increasing dose of oxygen invasion, at a point which probably corresponds to Vthc.

Mechanical Stress Evaluation of Si Metal–Oxide–Semiconductor Field-Effect Transistor Structure Using Polarized Ultraviolet Raman Spectroscopy Measurements and Calibrated Technology-Computer-Aided-Design Simulations

Mechanical Stress Evaluation of Si Metal–Oxide–Semiconductor Field-Effect Transistor Structure Using Polarized Ultraviolet Raman Spectroscopy Measurements and Calibrated Technology-Computer-Aided-Design Simulations

Mechanical Stress Evaluation of Si Metal–Oxide–Semiconductor Field-Effect Transistor Structure Using Polarized Ultraviolet Raman Spectroscopy Measurements and Calibrated Technology-Computer-Aided-Design Simulations

The mechanical stresses in Si metal–oxide–semiconductor field-effect transistors (MOSFETs) were evaluated by polarized UV Raman spectroscopy measurements and stress simulations. To calibrate stress parameters of the materials used in the Si MOSFETs, we compared measured and simulated Raman frequency shifts on the cleaved Si(110) surfaces of the MOSFETs. Consequently, we extracted intrinsic stress values of -400 MPa for a SiO2, -200 MPa for polycrystalline Si (poly-Si), 700 MPa for Ni silicide, 1250 MPa for a SiN tensile stress liner, and -3500 MPa for a SiN compressive stress liner by finding good agreement between the measured and simulated Raman shift distributions. To verify our stress simulation, we investigated the source/drain width dependences of Raman frequency shifts near the channel regions of Si MOSFETs by top-view Raman measurements. The calculated Raman frequency shifts agreed well with the results of polarized Raman measurements in terms of not only relative tendencies but also absolute Raman shift values.

Inversion-channel enhancement-mode GaAs MOSFETs with regrown source and drain contacts

The use of compound semiconductors as the channel material has recently drawn great attention because of its potential to solve the upcoming Si metal–oxide–semiconductor field effect transistor (MOSFET) scaling problem for device beyond 22 nm node. In this work, a method of fabricating inversion-channel enhancement-mode GaAs n-MOSFET by incorporating molecular beam epitaxy regrown source and drain regions is demonstrated. By using regrown contact layers to avoid high-temperature processes and, thus, preserve the integrity of the oxide–semiconductor interface, the structure allows the fabrication of self-aligned III–V-based MOSFET. The fabricated n-channel enhancement-mode GaAs MOSFET with a 4 μm gate length shows a record high transconductance of 75 mS/mm.

Variation of Threshold Voltage in Strained Si Metal–Oxide–Semiconductor Field-Effect Transistors Induced by Non-uniform Strain Distribution in Strained-Si Channels on Silicon–Germanium-on-Insulator Substrates

The variation of threshold voltage in metal–oxide–semiconductor field-effect-transistors (MOSFETs) fabricated on strained Si on SiGe-on-insulator (SGOI) substrates is evaluated. A large variation of the threshold voltage is observed for MOSFETs on SGOI formed by the conventional Ge condensation method. It is experimentally revealed that the variation of threshold voltage is attributable to the variation of strain in the Si channel layers. This variation is found to be correlated with the variation of the lattice spacing in the SGOI crystal layers, which is caused by non-uniform lattice relaxation in the SGOI layers during the condensation process. It is also found that the variation of the relaxation ratio of SGOI can be significantly suppressed by the two-step oxidation and Ge condensation method.

Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress

An experimental method to determine both the hydrostatic and shear deformation potential constants is introduced. The technique is based on the change in the gate tunneling currents of Si-metal oxide semiconductor field effect transistors (MOSFETs) under externally applied mechanical stress and has been applied to industrial n-type MOSFETs. The conduction band hydrostatic and shear deformation potential constants (Ξd and Ξu) are extracted to be 1.0±0.1 and 9.6±1.0eV, respectively, which is consistent with recent theoretical works.

Application of a self-sensing conductive probe for Si device imaging

For the evaluation of two-dimensional carrier profiles in semiconductor devices, we have developed a novel form of probe–sensor combined unit that uses an etched tungsten wire as a conductive probe, and commercially available quartz tuning fork as the force sensor. This unit has a self-sensing capability due to the piezoelectric effect of quartz tuning fork, thus obviating optical setup, and its conductivity is higher and more stable than that of conventional metal-coated Si cantilever. In addition, this probe–sensor combined unit is inexpensive and easy to use, when compared to the well-known optical methods of Si-based cantilever vibration detection system. Our scanning probe microscope using this probe–sensor combined unit is able to mapping the capacitive gradient signal (dC/dZ image) and internal damping of quartz tuning fork oscillation (dissipation image) while scanning the sample surface. In this letter, we show the results of visualization of the p–n junction locus of a Si metal–oxide–semiconductor field effect transistor in both dC/dZ and dissipation images.

Fluoride Resonant Tunneling Diodes Co-integrated with Si-MOSFETs

Resonant tunneling diodes (RTDs) composed of heteroepitaxial CaF2/CdF2/CaF2 structure grown on Si substrates were co-integrated with Si-metal oxide semiconductor field effect transistors (MOSFETs), and test circuits of the static random access memory (SRAM) cell were fabricated. The RTD structures were grown in the opened diode holes on the oxide film, where a high dose of phosphorus ions (P+) had been implanted. Surface roughening of ion-implanted Si before the fluoride growth due to an increase of the ion dose was investigated, and the optimum dose was determined. Normal operations of both fluoride RTD and Si-MOSFET in the fabricated circuit were obtained. Bistable operation was also observed for the circuit in which two RTDs were connected in series.

Characteristic length of hot-electron transport in silicon metal–oxide–semiconductor field-effect transistors

Characteristic length of hot-electron transport in an inversion layer at a Si surface is estimated by using lateral hot electron transistor, which has an upper gate and two lower gates. The inversion layer formed by biasing the upper-gate voltage is separated into three channel regions (the emitter, collector, and base) by the two lower gates. We find that the characteristic length depends on both the upper-gate voltage and the injection energy and ranges from 19 to 27 nm. These results show that hot electrons are affected by electron–electron scattering or surface–roughness scattering and that hot-electron transport plays a crucial role in Si metal–oxide–semiconductor field effect transistors with gate lengths of 20 nm or less.

Channel electron mobility dependence on lateral electric field in field-effect transistors

A method is described to measure the channel charge density-mobility product in field-effect transistors as a function of lateral channel field. From knowledge of the channel charge density, the channel carrier mobility-lateral field relation is determined. This method was applied to n-channel Si metal–oxide–semiconductor field–effect transistors. The channel charge density was determined at low lateral field as a function of gate-to-channel voltage from capacitance measurements and this value was corrected to account for electron saturation velocity effects at higher fields. The electron mobility-field results were obtained for lateral fields up to 2×105 V/cm, a factor of 5–10 larger than previously obtained, and were fit to the conventional empirical relation for mobility, μ=μlf[1+(μlfξL/vsat)β]−1/β, where μlf is mobility at small lateral fields, vsat is electron saturation velocity, ξL is the magnitude of the lateral channel field, and β is an empirical fitting parameter; a best fit to this relation was obtained for unity β and vsat of 4×106 cm/s.

Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal–oxide–semiconductor field effect transistor channels

Si/Si 0.64 Ge 0.36 /Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm2 V−1 s−1 for a sheet density of 6.2×1011 cm−2. The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 °C, commensurate with metal–oxide–semiconductor device fabrication.

The use of Kubo formula to examine low temperature transport limited by interface roughness and phonons in metal–oxide–semiconductor field effect transistors

An approach to study transport in semiconductors using the Kubo formula is developed and applied to Si metal–oxide–semiconductor field effect transistors (MOSFETs). It is known that interface roughness is an important source of scattering in a MOSFET device operating at high sheet charge concentration (∼1012 cm−2). However, in spite of its importance, due to the complexity of the problem very simple models based on the Born approximation are used to study transport. The Born approximation breaks down when the interface quality is poor and transport occurs in lower energy localized states (for example, at low temperature). In this article we present results of a numerical method based on a three-dimensional approach to examine the interface roughness effects on electronic spectrum as well as on transport. Using the approach suggested by the Kubo formula we solve for the electronic states in the presence of interface roughness. Kubo formula is then used to study the transport properties as a function of sheet charge density, interface roughness level, and temperature. The model can easily be applied to other problems where scattering effects are very strong, e.g., in amorphous semiconductor devices.

Electron transport properties of quantized silicon carbide inversion layers

Electron transport properties in SiC quantized inversion layers have been studied by means of a Monte Carlo procedure. It has been observed that the contribution of polar-optical phonon scattering produces a significant influence of the effective-electric field on the high longitudinal field transport regime, this being the main difference of SiC with respect to standard Si inversion layers. The energy- and momentum-relaxation times have been calculated and the results suggest that electron velocity overshoot effects are less important than in Si metal-oxide semiconductor field effect transistors. The electron mobility is not very different from their silicon counterparts, but the saturation velocity is higher.

Lithographic patterning of self-assembled films

This article discusses a new, general approach for fabricating surfaces with precise positional control of chemical functionalities utilizing direct patterning of self-assembled (SA) or- ganosilane monolayer films with lithographic exposure tools, including deep ultraviolet, x-ray, and e-beam sources. Lithographically patterned one- and two-component SA films have been used to selectively deposit or attach a wide variety of materials to surfaces, including catalysts, electroless metal films, proteins, cells, and organic moieties. Selectively metallized, patterned SA films have been employed to fabricate functioning Si metal–oxide–semiconductor field effect transistor test structures. The utility of patterned SA films for microelectronics, sensors, and other applications is discussed.

Boron redistribution in arsenic-implanted silicon and short-channel effects in metal–oxide–semiconductor field effect transistors

When a high dose of As is implanted (e.g., 25 keV, 3×1015 cm−2) into B-doped Si and the sample is subsequently annealed at 900 °C/5 min, pronounced segregation of the B into the implanted region occurs. This creates a B-depleted region beyond the As profile. It is demonstrated that the B segregation is driven primarily by the implantation induced damage rather than by As-B chemical and/or by electric field effects. The B segregation is nearly complete after a relatively low temperature (≲600 °C/30 min) anneal. Two-dimensional device simulations show that the B depletion observed here can account for ≂50 mV threshold voltage roll off (at a drain bias of 0.1 V) in a Si metal–oxide–semiconductor field effect transistor of 0.2 μm gate length.

Gate technology for 89 GHz vertical doping engineered Si metal–oxide semiconductor field effect transistor

The gate definition performed on a vertical doping engineered metal–oxide semiconductor field effect transistor is described. The fabricated gates were as narrow as 0.15 μm. For writing narrow gates, e-beam lithography and a chemically amplified negative resist SAL603 were used. The alignment between the gate level and underlying Nikon-printed levels was made using 0.8 μm deep trenched marks. The gate patterning was done with reactive ion etching (RIE) in CHF3 gas to etch a nitride layer which serves as a gate etch mask and subsequently in a Cl2 gas used to etch the polysilicon gate. A sidewall spacer was formed with a two step etch using CF4 RIE and CHF3 RIE after deposition of a 2000 Å TEOS film. After metallization the n-channel devices have measured excellent device characteristics.

Si metal–oxide semiconductor field effect transistor with 70-nm slotted gates for study of quasi-one-dimensional quantum transport

We have fabricated dual-gate Si metal–oxide semiconductor field effect transistor devices in which the lower gate is slotted and the upper gate, separated by 45 nm of SiO2, is planar. By appropriate adjustment of the potentials on the two gates, the field lines from the upper gate are pinched, creating an inversion layer about one-half the slot width. The resist patterning was done by x-ray lithography, using a mask that combined crystallographic-template/sidewall-shadowing techniques with UV lithography. The slotted lower gate was produced by lift-off. The metallization was a sandwich structure of Cr/W/Cr which permitted high-temperature annealing. Very high mobilities, ∼15 000 cm2 /V s at 4.2 K, were achieved as a result. The combination of high mobility and extremely narrow inversion channel (∼30 nm) yields very clear structure in the conductance as a function of gate voltage, which cannot be accounted for by either localization effects or universal conductance fluctuations. Although these oscillations may be related to one-dimensional subband effects, the magnetic field independence of the oscillations is not understood. At very high (12 T) magnetic fields an anomalous magnetoresistance has been seen.