Si Metal Oxide Semiconductor Devices Research Articles

Investigation of structural and electrical properties on substrate material for high frequency metal–oxide–semiconductor (MOS) devices

Hafnium oxide (HfO2) thin films were grown on cleaned P-type 〈1 0 0〉 Ge and Si substrates by using atomic layer deposition technique (ALD) with thickness of 8 nm. The composition analysis of as-deposited and annealed HfO2 films was characterized by XPS, further electrical measurements; we fabricated the metal–oxide–semiconductor (MOS) devices with Pt electrode. Post deposition annealing in O2 ambient at 500 °C for 30 min was carried out on both Ge and Si devices. Capacitance–voltage (C–V) and conductance–voltage (G–V) curves measured at 1 MHz. The Ge MOS devices showed improved interfacial and electrical properties, high dielectric constant (~19), smaller EOT value (0.7 nm), and smaller Dit value as Si MOS devices. The C–V curves shown significantly high accumulation capacitance values from Ge devices, relatively when compare with the Si MOS devices before and after annealing. It could be due to the presence of very thin interfacial layer at HfO2/Ge stacks than HfO2/Si stacks conformed by the HRTEM images. Besides, from current–voltage (I–V) curves of the Ge devices exhibited similar leakage current as Si devices. Therefore, Ge might be a reliable substrate material for structural, electrical and high frequency applications.

(Invited) Gate Stack Technology for Advanced AlGaN/GaN Mos-Hemt Power Devices

AlGaN/GaN high electron mobility transistor (HEMT) has gained much attention as next-generation high frequency and high power devices. Since AlGaN/GaN HEMT with Schottky gate is restricted in device application due to large gate leakage current and normally-on operation, metal-oxide-semiconductor (MOS) gate stack with deposited gate insulator has been widely investigated to overcome these limitations. Among various insulating materials, aluminum based oxide such as Al2O3 is one of the potential candidate because of its wide bandgap and high thermal stability. However, large amount of interface traps at MOS interfaces severely degrade both carrier mobility and threshold voltage (Vth) stability. Furthermore, significant electron injection into Al2O3 layer causing positive Vth shift was often observed for Al2O3/AlGaN/GaN MOS-HEMT. We have recently reported that N incorporation into Al2O3 (aluminum oxynitride) significantly reduces not only the negative fixed charges but also the electron traps in Si and SiC MOS devices. In this study, superior physical and electrical properties of AlON gate dielectrics on AlGaN/GaN substrates were demonstrated. We fabricated high-quality AlON/AlGaN/GaN MOS capacitors with improved stability against charge injection and a reduced interface state density. Moreover, the impact of nitrogen incorporation into the gate insulator will be discussed on the basis of results from physical characterizations.

Criteria for Plasmon-Enhanced Electron Drag in Si Metal–Oxide–Semiconductor Devices

Plasmons in the highly doped source and drain regions of silicon field-effect transistors can strongly drag channel electrons via long-range collective Coulomb interactions and cause deteriorations in overall device performances. To examine such interactions, two different methods have been published: 1) sophisticated device simulations and 2) carefully calibrated experiments. To provide a more transparent understanding, we propose a third method in terms of two criteria: 1) one for the occurrence of the plasmon resonance and 2) the other for the strength of the plasmons. The former is determined based on our published dragged mobility data due to the interface plasmons and the bulk plasmons in gate. The latter makes use of our more recently experimentally extracted potential fluctuations due to plasmons in crystalline silicon. The effects of the temperature on the criteria are considered. It is a straightforward task to confirm that for a channel density larger than approximately 5 × 1012 cm -2 , the source and drain plasmons act as key limiters in silicon device scaling. Therefore, the underlying device physics, modeling, simulations, experimental analyses, and data interpretation may be inaccurate if the limiting factors are not incorporated.

Linear energy transfer dependence of single event gate rupture in SiC MOS capacitors

Metal-oxide-semiconductor (MOS) capacitors were fabricated on n-type 4H silicon carbide (SiC) epitaxial layers grown on n-type 4H-SiC substrates, and the currents through the gate oxide of the MOS capacitors were measured under accumulation bias conditions during heavy-ion irradiation. Evaluation of the linear energy transfer (LET) dependence of the critical electric field (Ecr) at which dielectric breakdown occurred in these capacitors revealed that the reciprocal of Ecr (1/Ecr) increased linearly with increasing LET. The slope of LET dependence of 1/Ecr for SiC is lower than that for Si, suggesting that SiC MOS devices are less susceptible to single-event gate rupture (SEGR) than Si MOS devices. The limitation of previously proposed SEGR models based on SiO2 on Si is discussed, as is the importance of the physical parameters of the oxide and semiconductor materials (bandgap, carrier lifetime and mobility, etc.).

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

We report on experimental observations of room temperature low frequency capacitance-voltage (CV) behaviour in metal oxide semiconductor (MOS) capacitors incorporating high dielectric constant (high-k) gate oxides, measured at ac signal frequencies (2 kHz to 1 MHz), where a low frequency response is not typically expected for Si or GaAs MOS devices. An analysis of the inversion regions of the CV characteristics as a function of area and ac signal frequency for both n and p doped Si and GaAs substrates indicates that the source of the low frequency CV response is an inversion of the semiconductor/high-k interface in the peripheral regions outside the area defined by the metal gate electrode, which is caused by charge in the high-k oxide and/or residual charge on the high-k oxide surface. This effect is reported for MOS capacitors incorporating either MgO or GdSiOx as the high-k layers on Si and also for Al2O3 layers on GaAs(111B). In the case of NiSi/MgO/Si structures, a low frequency CV response is observed on the p-type devices, but is absent in the n-type devices, consistent with positive charge (>8 × 1010 cm−2) on the MgO oxide surface. In the case of the TiN/GdSiOx/Si structures, the peripheral inversion effect is observed for n-type devices, in this case confirmed by the absence of such effects on the p-type devices. Finally, for the case of Au/Ni/Al2O3/GaAs(111B) structures, a low-frequency CV response is observed for n-type devices only, indicating that negative charge (>3 × 1012 cm−2) on the surface or in the bulk of the oxide is responsible for the peripheral inversion effect.

Investigation of the band offsets caused by thin Al2O3 layers in HfO2 based Si metal oxide semiconductor devices

Ultrathin dielectric capping layers are a prominent route for threshold voltage control in advanced Si devices. In this work the position of an Al2O3 layer inside a HfO2-based stack is systematically varied and investigated following a low and a high temperature anneal. Electrical results are compared with a sub-nanometer resolution materials characterization, showing a diffusion of Al to the bottom HfO2 interface. A correlation is found between the presence of Al at the bottom interface and a flatband voltage increase. Based on these findings, we propose to use the position of the Al2O3 for fine-tuning the threshold voltage.

A simple microcontroller-based current electrometer made from LOG112 and C8051F006 for measuring current in metal–oxide–semiconductor devices

A microcontroller-based current electrometer built from LOG112 and C8051F006 system-on-a-chip has been developed for measuring current flowing through a MOS (metal–oxide–semiconductor) device. The Fluke 5100B series calibrator and a computer have been used to calibrate the electrometer. In order to examine the performance of the electrometer, Al|SrTiO3|Si and BS250 MOSFET-based MOS devices have been employed as devices under test and the Keithley 617 Programmable Electrometer has been applied as a reference. It has been found that the currents measured by the Keithley 617 Programmable Electrometer were reproduced very well by the developed electrometer.

Formation of misfit dislocations at the thin strained Si∕strain-relaxed buffer interface

Misfit dislocations at the strained Si∕SiGe strain-relaxed buffer interface are known to enhance leakage currents of strained Si metal oxide semiconductor devices. As we show in this letter, misfit dislocations at this interface might be generated even for Si thicknesses below the critical thickness for layer relaxation. The important parameter is the degree of relaxation of the strain-relaxed buffer. If the strain-relaxed buffer is not fully relaxed, threading dislocations can glide during thermal treatments. This results in misfit dislocations at the strained Si∕SiGe interface, because the threading dislocation segments within the strained Si are blocked by its tensile stress.

Introduction of Si∕SiO2 interface states by annealing Ge-implanted films

Nanocrystals embedded in SiO2 films are the subject of a number of recent works, mainly because of their potential usefulness in the fabrication of optoelectronic devices and nanocrystal memory structures. One interesting method for the fabrication of such nanocrystals is the ion implantation of segregating species into SiO2 films followed by heat treatment in order to induce nanocrystal formation. This method is both relatively simple and also compatible with the current MOS (metal-oxide-semiconductor) device technology. An unintentional effect can occur during the fabrication of nanocrystals using this method, namely a significant diffusion of the implanted species during annealing, away from the regions with the highest concentration. The Si∕SiO2 interface can be exposed to this diffusion flux. This can result in an altered interface and have a significant influence on electronic devices. Here, we report on ion implantation of Ge into SiO2 on Si followed by annealing under conditions, resulting in Ge accumulation at the Si∕SiO2 interface as determined by secondary-ion mass spectroscopy analysis, transmission electron microscopy with energy dispersive analysis of x-rays, and Rutherford backscattering spectrometry. The accumulation of Ge at the Si∕SiO2 interface has also been reported before. The resulting effect on the electronic structure of the interface is a priori unknown. We have fabricated MOS capacitors on the sample structures and their capacitance-voltage characteristics were measured and analyzed. We measure an interface state density around 1×1012cm−2, which is high compared to standard Si MOS devices. We discuss the results in terms of the previous electrical measurements on Ge-oxide interfaces and SiGe interfaces, which also can yield a high interface state density. The specific conditions we report result in a sufficiently low Ge concentration that nanocrystals are not segregated in the SiO2 film, while Ge still accumulates at the Si∕SiO2 interface after annealing.

Thermal behavior of deep levels correlated with iron in silicon metal-oxide-semiconductor structure

Thermal behavior of deep levels correlated with iron in Si MOS (metal-oxide-semiconductor) structure has been studied by isothermal capacitance transient spectroscopy. As a result, it is shown that interstitial iron scarcely affects the interface trap (Nt) of MOS structure. This is made clear by measuring Nt of Si MOS diodes containing iron impurity, the interstitial component of which is controlled by low temperature annealings. In addition, the low temperature (400 °C) annealing decreases interstitial iron concentration as well as interface trap density. This phenomenon is very lucky for Si MOS devices.

Accurate Determination of Defects in the Gate Oxide of Si Metal Oxide Semiconductor Devices by Propane Infiltration

A new technique has been developed to determine accurately the location and distribution of defects in layers thermally grown on Si substrates. The technique utilizes selective propane (5% in ) carbonization of the Si surface exposed by oxide pinholes to form well‐defined islands of at the interface. This propane infiltration was performed at 1300°C for times of 2–90 s at reduced pressure (5 Torr). The islands formed at the interface are circular, with a diameter directly related to the size of the oxide pinhole at each location. For a 1000 Å oxide and 15 s reaction time, the island (and hence defect) density was typically ∼700/cm2.