Si SiGe Research Articles

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I−V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (V t), drain current (I ON), OFF current (I OFF), and ON-OFF current ratio (I ON/I OFF) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (g m), output transconductance (g ds), gain (g m/g ds), transconductance generation factor (TGF), cut-off frequency (f T), maximum oscillation frequency (f max), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (g m2, g m3), voltage intercept points (VIP2, VIP3) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more g m and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.

A new line tunneling SiGe/Si iTFET with control gate for leakage suppression and subthreshold swing improvement

This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

A Simulation Study of SiGe Shell Channel CFET for Sub-2-nm Technology Nodes

In this article, a SiGe shell complementary FET (CFET) composed of an inversion mode (IM) nFET and a junctionless accumulation mode pFET under 2-nm (N2) and 1.5-nm (N1.5) technology nodes was studied for the characteristics of a single device and the CMOS logic circuit using 3-D numerical simulation. A comparison study between Si shell nanosheet and SiGe shell CFET with a Ge mole fraction in the range of 0.5–0.9. Compared with the Si shell nanosheet (NS), the SiGe shell CFET improves the ON-state current, transconductance, transition frequency, and intrinsic delay up to 29%, 32%, 31%, and 21%, respectively. Due to the mobility improvement in SiGe shell CFET, the fall time, rise time, propagation delay, and maximum operating frequency of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {Si}_{{0.5}}\text {Ge}_{{0.5}}$ </tex-math></inline-formula> shell CFET are also improved up to 2%, 43%, 3%, and 3%, respectively, compared with their Si shell counterparts. This SiGe shell CFET has a lower parasitic RC, a smaller layout area, and better analog and digital performance at the sub-2-nm technology node. This makes it a promising architecture for future high-performance CMOS logic applications.

(Digital Presentation) Strong Room-Temperature EL Emissions from Strained Sige/Ge-on-Si (111) LEDs

Introduction In recent years, encryption technology has become more and more important, and the method to use the circular polarized light in optical communications has been proposed. Spin LEDs are expected as on-chip circular polarized light generating devices, and we have been focusing on a Ge as an active material because it is capable of being monolithically integrated on a Si substrate and emitting light in the telecommunications wavelength band. Particularly, the (111) surface orientation of Ge allows for the epitaxial growth of high-quality ferromagnetic materials on Ge, making it possible to inject spin-polarized electrons from ferromagnetic materials into Ge (111) [1]. Furthermore, it has been proven that the use of strained-SiGe can increase the spin lifetime because of its ability to suppress intervalley scattering [2]. In this study, we fabricate strained-SiGe/Ge-on-Si (111) LEDs and obtain very strong EL emissions at room temperature. Experimental The sample was prepared using a solid source molecular beam epitaxy (MBE). First, a high-quality tensile-strained Ge layer was grown on a Si (111) substrate using two-step growth method, where a Ge buffer layer of 40 nm was grown on a p-type Si (111) substrate at a temperature of 350℃ and a Ge layer of 500 nm was grown at 700℃. Secondly, a Si0.15Ge0.85 layer of 40 nm and a P-doped Ge layer of 500 nm were grown at lower temperature of 350℃ to prevent relaxation of the SiGe. After the growth of the p-i-n structure, a P delta-doping layer of 2×1014 cm-2 was inserted to obtain a low resistivity Ohmic contact. Before P delta-doping, an ultra-thin Si (UT-Si) layer of 2 monolayers was inserted in order to avoid surface segregation of P atoms [3]. Finally, 7 nm thick Ge was grown for the capping. The fabricated multilayers were defined into a mesa diode by photolithography and reactive ion etching. AuSb and AuGa were deposited as top and back contacts, respectively. Results and Discussions Current-voltage output characteristics were evaluated and good diode characteristics were obtained. Figure 1 shows the room temperature EL spectra for the Si0.15Ge0.85/Ge LEDs with various injected currents. It was found that strong EL emissions covering the communication wavelength band of 1500-1600 nm was obtained. The EL peak intensity increases with the injected current and it is drastically enhanced above 350 mA as shown in inset of Fig. 1. We consider that recombination efficiency can be improved by the strained Si0.15Ge0.85 layer. While exact light emission wavelengths cannot be known with the current experiments due to the detector upper limit, characterizations in the longer wavelength range are now under investigation. Moreover, we expect further enhancements of EL intensity by introducing Si0.15Ge0.85/Ge multiple quantum wells in the active layer. It is also expected that by changing compositions of Si and Ge in SiGe, we can control the emission wavelength range, indicating that the SiGe/Ge LEDs are very attractive for application to on-chip circular polarized LEDs.This work was supported in part by Grant-in-Aid for Scientific Research (19H02175, 19H05616, 20K21009) from MEXT, Japan.[1] K. Hamaya et al., J. Phys. D: Appl. Phys. 51, 393001 (2018).[2] T. Naito et al., Phys. Rev. Appl. 13, 054025 (2020).[3] M. Yamada et al., Appl. Phys. Lett. 107. 132101 (2015). Figure 1

(Invited) SiGe/SOI System: Mechanisms of Condensation and Strain Relaxation

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

Prismatic Ge-rich inclusions in the hexagonal SiGe shell of GaP-Si-SiGe nanowires by controlled faceting.

Formation of Ge-rich prismatic inclusions in the hexagonal SiGe shell of GaP-Si-SiGe nanowires is reported and discussed in relation to a growth model that explains their origin. An accurate TEM/EDX analysis shows that such prisms develop right on top of any {112[combining macron]0} facet present on the inner GaP-Si surface, with the base matching the whole facet extension, as large as tens of nanometers, and extending within the SiGe shell up to a thickness of comparable size. An enrichment in Ge by around 5% is recognized within such regions. A phase-field growth model, tackling both the morphological and compositional evolution of the SiGe shell during growth, is exploited to assess the mechanism behind the prism formation. A kinetic segregation process, stemming from the difference in surface mobility between Ge (faster) and Si (slower), is shown to take place, in combination with the evolution of the SiGe shell morphology. Actually, the latter moves from the one templated by the underlying GaP-Si core, including both {101[combining macron]0} and {112[combining macron]0} facets, to the more energetically convenient hexagon, bounded by {101[combining macron]0} facets only. Simulations are shown to accurately reproduce the experimental observations for both regular and asymmetric nanowires. It is then discussed how a careful control of the GaP core faceting, as well as a proper modulation of the shell growth rate, allows for direct control of the appearance and size of the Ge-rich prisms. This tunability paves the way for a possible exploitation of these lower-gap regions for advanced designs of band-gap-engineering.

(Plenary) The Revival of Compound Semiconductors and How They Will Change the World in a 5G/6G Era

Compound semiconductor devices have always intrigued the semiconductor industry due to their high intrinsic mobilities and the heterostructure engineering enabled by those materials. While CMOS has been the vehicle pushing the industry to ever smaller devices, better performance and of course reduced cost, the unique properties of compound semiconductor devices are finding renewed interest in an era where an increasing amount of data is being sent around, stored and analyzed. While several applications like photonics, high-power electronics and image sensors also benefit from enabling a variety of III-V materials and devices, specifically, in the RF Front-End Modules of 5G radio chips [1], these materials allow to address the challenges related to speed, efficiency and output power needed for this next generation wireless communication standard. And while 5G is in full deployment, with first addressing the sub-6GHz frequency bands and in a later phase the mm-wave frequency bands, first publications are already appearing on 6G, where even higher frequencies (beyond > 100GHz) will be targeted [2].GaN [3] and InP-based devices [4] have a clear performance advantage over Si CMOS and SiGe HBT/BICMOS, but their lower integration potential, still restricted to smaller size substrates and lab-like processing today, is one of the key limitations for adopting those technologies for high-volume 5G and 6G applications. Upscaling those devices to a 200mm/300mm Si platform will be a first step to improve yield and maturity and increase complexity. In a second phase, upscaling and maturing these technologies will allow to co-integrate these devices, usually quite dissimilar to CMOS, with advanced Si technology nodes and provide a fully integrated heterogeneous system.In this talk, we will review the status and progress toward integrating these devices on a CMOS-compatible platform.

Theoretical Simulation of Backscattering Electron Coefficient for SixGe1-x/Si Heterostructure as a Function of Primary Electron Beam Energy and Ge Concentration

Abstract: This study aims to investigate the backscattering electron coefficient for SixGe1-x/Si heterostructure sample as a function of primary electron beam energy (0.25-20 keV) and Ge concentration in the alloy. The results obtained have several characteristics that are as follows: the first one is that the intensity of the backscattered signal above the alloy is mainly related to the average atomic number of the SixGe1-x alloy. The second feature is that the backscattering electron coefficient line scan shows a constant value above each layer at low primary electron energies below 5 keV. However, at 5 keV and above, a peak and a dip appeared on the line scan above Si-Ge alloy and Si, respectively, close to the interfacing line. Furthermore, the shape and height of peak and dip broadening depend on the primary electron energy and incidence position with respect to the interfacing line. The last feature is that the spatial resolution of the backscattered signal at the interfacing line is improving by decreasing the primary electron energy (below 5 keV) and the shared element (Si) concentration. On the other hand, a poor compositional contrast has been shown at low primary electron energy below 5 keV. For energies above 5 keV, the spatial resolution becomes weak. These results can be explained by the behavior of the incident electrons inside the solid (interaction volume), especially at a distance close to the interfacing line and their chance to backscatter out of the sample. In general, a good compositional contrast with a high spatial resolution can be achieved at primary electron energy equal to 1 keV. Keywords: Monte Carlo model, Backscattering electron coefficient, Si-Ge/Si, Elastic scattering, Spatial resolution, Compositional contrast.

(Invited) New Strategies to Produce Light Emitters with Si-based Nanostructures

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device

In this work, SiGe Fin formation technique using shallow trench isolation (STI) first or STI last strategy for the high mobility channel FinFET device is systematically investigated. A 20 nm width and 35 nm height high crystalline quality of the Si0.7Ge0.3 Fin formation for STI first scheme is demonstrated by utilizing a new developed Si Fin etching, Si Fin recess and SiGe selective epitaxial growth process. For the STI last strategy, a novel chemical mechanical planarization (CMP) treated three-layer SiGe strain relaxed buffer (SRB) is successfully fabricated and a 50 nm high crystal quality and atomically smooth surface Si0.5Ge0.5 layer on this SRB is attained. Moreover, a spike annealing is employed to avoid the Si0.5Ge0.5 Fin oxidation during STI densification with an acceptable STI etching rate. However, both a spike annealing and a lower temperature of traditional furnace at 850 °C or 750 °C suffer micro-trench issue during the Fin reveal process. Therefore, a new developed process, named as STI recess first, is developed to resolve both thermal instability and micro-trench issue at the same time. A minor Si0.5Ge0.5 Fin loss with a sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for STI last scheme is realized by utilizing this new developed STI recess first process.

Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique

In this study, tunnel field-effect transistor (TFET) which has surface Ge-rich SiGe nanowire as a channel has been demonstrated. There are improvements in terms of on-current and subthreshold swing (SS) comparing with control groups (constant Ge concentration SiGe TFET and Si TFET) fabricated by the same process flow except for the channel formation step. In order to obtain the concentration-graded SiGe channel, Ge condensation method which is a kind of oxidation is adopted. The rectangular shape of the channel becomes a rounded nanowire through the Ge condensation process. The TFET with the concentration-graded SiGe channel can improve drive current due to a smaller band gap at the Ge-condensed surface of the channel compared to Si or non-condensed SiGe channel TFET.

Incorporation of Ge on High K Dielectric Material for Different Fabrication Technologies (HBT, CMOS) and Their Impact on Electrical Characteristics of the Device

The paper is composed of distinct reviews on various fabrication technologies of the CMOS family and the characterization of MOS capacitors. The initial part of the article essentially presents a systemic review on an already conducted work on different fabrication technologies such as Si MOSFET, SiGe HBT, and InP HBT. Device and circuit-level performance for broadband and tuned millimetre-wave applications is discussed in detail relative to the underlying CMOS technologies. The comparison is made for various performance metrics for 180 nm, 130 nm, and 90 nm n-MOSFET devices for SiGe and InP HBTs. In the latter part of the study, a comprehensive review on a previously conducted research on electrical and physical characterization of metal-oxide-semiconductor (MOS) capacitors fabricated on a 2.5 μm epitaxial germanium layer grown on (100) silicon substrate is undertaken. The focus and crux of the study is the influence of germanium surface preparation on MOS electrical characteristics. It is observed that predielectric (HfO) deposition annealing in NH3 ambience results in the performance upgradation in critical and key parameters such as equivalent oxide thickness and the gate leakage current.

A New Paradigm in High-Speed and High-Efficiency Silicon Photodiodes for Communication—Part I: Enhancing Photon–Material Interactions via Low-Dimensional Structures

Photodetectors (PDs) used in communication systems require ultrafast response, high efficiency, and low noise. PDs with such characteristics are increasingly in demand for data centers, metro data links, and long-haul optical networks. In a surface-illuminated PD, high speed and high efficiency are often a tradeoff, since a high-speed device needs a thin absorption layer to reduce the carrier transit time, whereas a high-efficiency device needs a thick absorption layer to compensate for the low absorption coefficient of some semiconductors such as Si and Germanium (Ge) or SiGe alloys at wavelengths near the bandgap. In this part of this review, we present the recent efforts in enhancing the photon–material interactions by using low-dimensional structures that can control light for more interaction with the photoabsorbing materials, slow down the propagation group velocity and reduce surface reflection. We present recent demonstrations of high-speed PDs based on nanostructures enabled by both synthetic bottom-up or transformative top-down processing methods. In particular, we detail a CMOS-compatible ultrafast surface-illuminated Si PD with 30-ps full-width at half-maximum, and >50% efficiency at 850 nm. A complementary discussion on device challenges and the integration of low-dimensional structures will be presented in the part II of this review.

SiGe Heterojunction FinFET Towards Tera-Hertz Applications

In this work, a novel structure FinFET having an ultra-thin SiGe shell channel forming a heterojunction with Si core is proposed and characterized, with an emphasis on high-speed operation capability in the tera-hertz (THz) regime, by 3-dimensional (3-D) device simulation. The proposed device is operated in the p-type enhancement mode and the ultra-thin SiGe channel confines the mobile holes very effectively by the help of the valence band offset (VBO) between SiGe channel and Si core. The simulations with multiple drift and diffusion models and quantum mechanical models for higher accuracy allow to predict the minimum channel thickness and Ge content of 2 nm and 40%, respectively, for suppressing the hole leakage outflowing over the VBO. Also, scalability was checked down to 5 nm for achieving the upcoming logic technology nodes. Cut-off frequency (f T ) and maximum oscillation frequency (fmax) are obtained to be 240 GHz and 1.04 THz at a low drive voltage as −0.7 V, respectively.

A Precision SiGe Reference Circuit Utilizing Si and SiGe Bandgap Voltage Differences

Silicon–germanium (SiGe) BiCMOS technology platform provides designers with a unique opportunity to have access to both Si–Si and SiGe–Si p-n junctions. By taking advantage of the coexistence of these two p-n junctions, this paper presents a new temperature compensation technique for SiGe reference circuits. The source of the appearance of curvature in the thermal characteristics of reference circuits is due to the fact that the temperature-dependent nonlinearities in the base–emitter junction are not completely canceled across the temperature range of interest. Here, it is shown that under specific biasing conditions, the two Si–Si and SiGe–Si p-n junction voltages exhibit similar nonlinear temperature dependences. As such, a two-step temperature compensation technique is proposed: first, via a weighted subtraction of two currents, one proportional to the base–emitter junction of Si BJT and the other proportional to the base–emitter junction of SiGe heterojunction bipolar transistor, major nonlinear temperature-dependent terms are canceled; second, via the addition of a proportional to the absolute temperature current, the remaining linear temperature-dependent term is canceled. As a result of this two-step temperature compensation technique, an output voltage proportional to the difference of the bandgap voltages of Si and SiGe can be obtained. The proposed compensation technique is utilized to implement a precision reference circuit in IBM’s SiGe BiCMOS 8HP technology. Measurement results verify the stability of the circuit against temperature variations. As the generated output voltage of the circuit is proportional to the difference of Si and SiGe bandgap voltages, the proposed circuit can be utilized to experimentally evaluate the Ge-induced bandgap offset in a given SiGe technology platform.

Impurity-Driven Two-Dimensional Spin Relaxation Induced by Intervalley Spin-Flip Scattering in Silicon

Through the theoretical study of electron spin lifetime in the 2DEG of doped Si, we highlight a dominant spin relaxation mechanism induced by the impurity central-cell potential near an interface via intervalley electron scattering. At low temperatures and with modest doping, this Yafet spin flip mechanism can become much more important than the Dyakonov-Perel spin relaxation indcued by the structural Rashba spin-orbit coupling field. As the leading-order impurity-induced spin flip happens only between two non-opposite valleys in Si, two-dimensional electron gas (2DEG) systems in Si MOSFETs or SiGe heterostructures are a natural platform to test and utilize this spin relaxation mechanism due to the valley splitting near the interface and its tunability by electrical gating or applied stress. Our proposed new spin relaxation mechanism may explain a part of the spin relaxation contribution to Si-based 2DEG systems.

(Invited) Processing Technologies for Advanced Ge Devices

With proceeding CMOS device scaling, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons (e.g. to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow FIN structures, as well as doping diffusion and material intermixing). Different aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FINFET design to a nanowire FET design (also called Gate All Around FET). In this presentation we will address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures. Recently, we described the issue of Ge thermal instability against surface migration during selective epitaxial growth (SEG) of Ge by means of Chemical Vapor Deposition (CVD) in extremely narrow channels isolated by SiO2 [1]. Above a critical growth temperature filling of narrow channels is prohibited by Ge migration over the surface, due to the high Ge chemical potential in such narrow channels. The design of the FIN structure affects the maximal allowable growth temperature. This is critical as maintaining material quality sets a lower limit on the growth temperature [2]. Similar limitations need to be taken into account for the SEG of compressive strained Ge on top of a SiGe strain relaxed buffer (SRB). In addition, the reduced STI depth as used for high density FINs restricts the thickness of the SRB layer. The use of a V-shaped Si recess, combined with the deposition of a Ge-rich SiGe seed layer before the SRB growth, allows to reduce the Si0.3Ge0.7SRB thickness down to ~55nm while maintaining full strain relaxation (Fig. 1a). To investigate the strain state in more detail, reciprocal space maps (RSMs) were performed both along (longitudinal) and across (transverse) the fins [3,4]. From the RSMs, it is clear that the SiGe SRBs are relaxed with respect to the Si substrate. The Ge cap layer is uniaxially strained along the fins, with some relaxation occurring across the fins (Fig. 1b,c). An ultrathin Si layer is typically used to passivate the Ge surface in the high k gate module. The risk for Ge surface reflow, which in turn would lead to a (partial) relaxation of the strained Ge layer, sets the need to use high order Si-precursors such as Si3H8 and Si4H10to enable epitaxial growth at the required extremely low Si growth temperatures (< 350 °C) [4,5]. Horizontal gate all around (GAA) FETs are being considered a next logical step in scaling of Fin FETs for the 7 and 5 nm technological nodes. Their production promises little deviation from a standard Fin FETs processing flow and dramatic improvement of electro-static properties. In order to produce GAA FETs a stacking of two materials, typically Si/SiGe or SiGe/Ge, is used. An ultimate scaling of this technology assumes use of either Si or Ge and SiGe with high Ge contents close to 50%. Growth of such Si/SiGe or Ge/SiGe stacks with a large lattice mismatch is challenging since it is can only be done at low temperatures to avoid strain relaxation which would go together with defect incorporation. The use of higher order precursors allows to deposit fully strained and defect free Si/Si0.6Ge0.4 and Ge/Si 0.35 Ge 0.65 stacks with sharp interfaces between layers (Fig. 2), which are the most important requirements for GAA production. It enables us to demonstrate GAA FETs made of vertically stacked horizontal nanowires with excellent short-channel characteristics [8]. Acknowledgements: The imec core CMOS program members, European Commission, local authorities and the imec pilot line are acknowledged for their support. Epi layers are grown in EpsilonTM3200 and IntrepidTMXP systems from ASM. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases and Bruker Semiconductor Division for their kind support in XRD characterization of high mobility materials implemented in complex device architectures.

Analysis on temperature dependent current mechanism of tunnel field-effect transistors

In this paper, the total drain current (ID) of a tunnel FET (TFET) is decomposed into each current component with different origins to analyze the ID formation mechanisms of the TFET as a function of gate voltage (VGS). Transfer characteristics are firstly extracted with fabricated Silicon channel TFETs (Si TFETs) and silicon germanium channel TFETs (SiGe TFETs) at various temperatures. The subthreshold swings (SS) of both Si TFETs and SiGe TFETs get degraded and the SSs of SiGe TFETs get degraded more as temperature becomes higher. Then, all the IDs measured at various temperatures are decomposed into each current component through technology computer aided design (TCAD) simulations with a good agreement with experimental data. As a result, it is revealed that Shockley–Read–Hall (SRH) recombination mainly contribute to the ID of a TFET before band to band tunneling (BTBT) occurs. Furthermore, the SS degradation by high temperature is explained successfully by the SRH recombination with electric field dependence.

Application of Pelletron Accelerator to Study High Total Dose Radiation Effects on Semiconductor Devices

Silicon bipolar junction transistors (BJTs), Silicon-germanium heterojunction bipolar transistors (SiGe HBTs) and metal oxide semiconductor (MOS) devices are the key components of BiCMOS integrated circuits. The semiconductor devices need to withstand very high total doses (100’s of Mrad) for reliable operation of electronic circuits for 8-10 years of LHC operation. The study of radiation tolerance of semiconductor devices up to 100 Mrad of total dose takes longer time with conventional60Co gamma, proton and electron irradiation facilities and the effects due to these radiations are well understood. Hence it is important to study the effects of heavy ion irradiation on various semiconductor devices. The irradiation time decreases with increasing linear energy transfer (LET) of incident radiation and LET increases with atomic number of the impinging ions. But it is essential to understand the mechanism of energy transfer by different heavy ions in semiconductor devices. Therefore, here we give an overview of different heavy ion interactions with Si BJTs, MOSFETs and SiGe HBTs by primarily focusing on the electrical characteristics of these devices before and after ion irradiation. We show that the irradiation time needed to reach very high total dose can be reduced by using Pelletron accelerator facilities instead of conventional irradiation facilities.

Effects of low-temperature Si buffer thickness and SiGe oxidation on sensitivity of Si1−xGex nanowire

Si1−xGex nanowire biosensors are attractive for their high sensitivity due to the large surface-to-volume ratio, high carrier mobility, and silicon compatibility. In this work, we study the effect of the thickness of the low-temperature Si (LT-Si) buffer layer on an insulator on the sensitivity of oxidized Si1−xGex nanowire samples with different Ge contents by increasing the Si buffer thickness from 20 to 60 nm. 3-Aminopropyltrimethoxysilane (APTMS) was used as a biochemical reagent. It was demonstrated that, with the proper Ge content and LT-Si buffer thickness, the sensitivity of the Si1−xGex nanowire is high and it can be further improved by Si1−xGex oxidation. This can be attributed to the reduction of the diameter to the nanometer order, which gives rise to an increased surface-to-volume ratio and further enhances the sensitivity of the biosensor.