SiGe Devices Research Articles

Effects of electron irradiation on SiGe devices

The degradation and the recovery behavior of the device performance for SiGe diodes and p-MOSFETs irradiated by 2-MeV electrons are reported. For diodes, it is noted that both the reverse and forward current increase by irradiation. An interesting observation is that the forward current decreases after irradiation for a forward voltage larger than ~ 0.7 V. This reduction can be explained by an increased resistivity of the Si substrate. The degradation recovers by thermal annealing after irradiation. For a fluence of 1 × 10 15 e/cm 2, the diode performance almost recovers to the initial condition after 250 °C annealing. For the transistors, after irradiation, a slight negative shift of the threshold voltage and a decrease of the drain current for input and output characteristics have been observed together with a decrease of hole mobility. This is mainly due to the increase of the threshold voltage induced by positive charge trapping in the gate oxide.

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.

1/ f noise study on strained Si 0.8Ge 0.2 p-channel MOSFETs with high-k/poly Si gate stack

The study of the low frequency (1/ f) noise of strained Si 0.8Ge 0.2 p-channel MOSFETs with poly Si/HfSiO x gate stacks is presented. Apart from the reduced threshold voltage, improved maximum transconductance and increased low-field mobility offered by the strained SiGe, the 1/ f noise was observed to be considerably lower than in the Si control devices. The 1/ f noise characteristics were likely originated by carrier number fluctuations (Δ n model) for both the strained SiGe and Si control pMOSFETs. This is consistent with the proposed model for high-k MOSFETs based on correlated number-mobility fluctuations theory. Despite the much worse high-k gate stack quality characterized by gate leakage and charge pumping, the relative reduction (up to 10×) in the noise for the strained SiGe over Si control with high-k is preserved, as was observed in the past for strained SiGe and Si control devices having SiO 2 gate dielectric, likely attributed to the existence of the Si cap layer.

New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate

Length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are systematically investigated. In the non-SiGe devices, the LOD effect is dominated by the STI stress and shows a little dependence of dummy poly gates. However, in the SiGe device, the LOD effect is strongly dependent on the location of the dummy poly gate. For dummy poly gate located outside the active area, the compressive stress from the SiGe S/D dominates the LOD effect, but for dummy poly gate located within the active area, the LOD effect is controlled by both the SiGe S/D stress within the dummy gate and the STI stress. The mechanisms of our new observations are analyzed with TCAD simulations.

Highly Efficient Monolithic Class E SiGe Power Amplifier Design at 900 and 2400 MHz

This paper discusses the impact of transistor performance and operating frequency on the design of monolithic highly efficient RF SiGe power amplifiers (PAs) using on-chip lump-element passives and/or bondwires to approximate the class E switching conditions. Single-stage SiGe PAs were designed and fabricated using both high-breakdown and high- fT devices targeting for the highest power-added-efficiency (PAE). The PAs designed using high-breakdown devices with on-chip tank inductors exhibit similar gain and PAE as those of high-fT devices, but capable of withstanding significantly higher supply voltages and deliver larger output power (> 23 dBm) more reliably. PAE of 68% (900 MHz) and 40% (2.4 GHz) was achieved from these highly integrated suboptimal PAs without using any off-chip matching. The degraded PAE at 2.4 GHz versus 900 MHz is shown to be caused by increased effective ground inductance parasitics, higher loss from both low-Q on-chip tank inductor and increased SiGe device switching loss with reduced power gain. Design insights on how to improve PAE of SiGe PAs at higher RF frequencies are discussed, as we increased the measured PAE of the class E PAs to an impressive 62-65% range at 2.3-2.4 GHz, which is among the best reported in the literature for Si-based monolithic PAs.

Opportunities and Challenges for Germanium and Silicon-Germanium Channel p-FETs

The electrical behavior of SiGe and pure Ge channel p-FET devices will be presented and discussed in this paper. By fabricating short channel SiGe, relaxed Ge and strained Ge channel devices with scaled high-κ/metal gate stacks, we demonstrate three main advantages of using these types of devices: i) more aggressive TINV scaling of the gate dielectric due to lower temperature processing, ii) band gap engineering to allow better control of threshold voltage and possibly iii) lower external resistance due to the higher B activation in these materials. The main drawback inherent to relaxed Ge and biaxially strained Ge and SiGe channels is that the ability to have improved transport properties without the need for external stressors always seems to come with a large penalty in off state leakage. The ION and IOFF in these devices are compared to recent work by others and a general trend is observed.

Influence of Interfacial Oxygen and Carbon on Misfit Dislocation Generation in SiGe Epitaxial Layers

The influence of interfacial oxygen (O) and carbon (C) at the SiGe epi/Si interface on misfit dislocation generation and their impact on embedded SiGe device performance were studied. It is found that the interfacial O and C increased the dislocation nuclei, and degraded the channel hole mobility, resulting in the degradation of its device performance. We concluded that it is indispensable to realize not only the low temperature SiGe growth but also the low temperature in-situ precleaning to improve device performance. By using the low temperature SiGe process at 550{degree sign} C including in-situ precleaning and SiGe growth, high device performance such as saturation drain current (Ion) of 765 μA/μm were achieved at off current (Ioff) of 100 nA/μm at drain bias (VDD) = 1.0 V by suppressing of dislocation generation.

A study of low energy phosphorus implantation and annealing in Si:C epitaxial films**This paper was first presented at the 3rd International SiGe Technology and Device Meeting (Princeton, New Jersey, USA, 15–17 May 2006) (ISTDM 2006).

The effect of phosphorus implantation and thermal annealing on properties of Si:C epitaxial films was investigated. High resolution x-ray diffraction analysis and secondary ion mass spectroscopy indicated that spike annealing only causes slight loss of substitutional carbon. Phosphorus implantation, even with low energy, could cause surface damages and loss of substitutional carbon. Although spike annealing effectively activates implanted phosphorus, it also results in significant substitutional carbon loss (from 1.2% to less than 0.5%) within the phosphorus diffused layer. The interaction of carbon and phosphorus resulted in a junction profile as abrupt as with 3 nm/decade.

Surface treatments of SiGe for scanning tunneling microscopy/spectroscopy and characterization of SiGe p-n junction

Hydrogen-termination of SiGe(001) surfaces for scanning tunneling microscopy/spectroscopy (STM/STS) measurements was realized by optimizing the chemical treatment. It was found that the chemical oxidation with H2SO4 made the SiO2∕SiGe interface smooth and that the resultant hydrogen-terminated surface treated in the HF+HCl solution had few surface states in the band gap. This surface enabled the authors to evaluate the electrical properties of SiGe by STM/STS. Using the chemical method developed here, STM images of SiGe p-n junctions clearly visualized the existence of the depletion region. Furthermore, the distribution of the local electric properties of SiGe p-n junctions could be revealed with the spatial resolution better than 5×5nm2. It is concluded that STM/STS is a powerful technique to evaluate the local properties of Si∕SiGe devices.

Liquid phase deposition silicon dioxide for surface passivation in SiGe metal-semiconductor-metal photodetectors

A low temperature (50 °C) thin oxide passivation layer has been employed to substantially suppress the dark current of SiGe planar metal-semiconductor-metal photodetectors (MSM-PDs). The low temperature oxide layer was prepared by using liquid phase deposition (LPD) process and deposited in regions between the interdigitated electrodes of MSM-PDs. A four time improvement in the dark current of the passivated SiGe device was achieved. The introduction of LPD-oxide passivation layer is believed to suppress surface states situated on SiGe surface and therefore reduce surface leakage. Additionally, such a thin oxide (15 nm) passivation layer did not affect the optical performance of passivated MSM-PDs.

Gate leakage mechanisms in strained Si devices

This work investigates gate leakage mechanisms in advanced strained Si∕SiGe metal-oxide-semiconductor field-effect transistor (MOSFET) devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure, and device processing on gate oxide leakage characteristics are analyzed in detail. In state of the art MOSFETs, gate oxides are only a few nanometers thick. In order to minimize power consumption, leakage currents through the gate must be controlled. However, modifications to the energy band structure, Ge diffusion due to high temperature processing, and Si∕SiGe material quality may all affect gate oxide leakage in strained Si devices. We show that at high oxide electric fields where gate leakage is dominated by Fowler-Nordheim tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. This is a direct result of strain-induced splitting of the conduction band states. However, for device operating regimes at lower oxide electric fields Poole-Frenkel emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Gate oxide interface trap density exhibits a dissimilar behavior and is highly sensitive to Ge atoms at the oxidizing surface, degrading with increasing thermal budget. Consequently advanced strained Si∕SiGe devices are inadvertently subject to a potential tradeoff between power consumption (gate leakage current) and device reliability (gate oxide interface quality).

High performance germanium MOSFETs

Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge has been achieved with its native oxynitride (GeO x N y ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (∼2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4× mobility enhancements over bulk Si devices and >10× BTBT reduction over surface channel strained SiGe devices.

Modeling of SiGe Devices Using a Self-Consistent Full-Band Device Simulator Which Properly Takes into Account Quantum-Mechanical Size Quantization and Mobility Enhancement

We examine performance enhancement of p-channel SiGe devices using our recently developed particle-based device simulator that takes into account self-consistently the bandstructure and the quantum mechanical space-quantization and mobility enhancement (due to the smaller 2D density of states function) effects. We find surface roughness to be the dominant factor for the bad performance of p-channel SiGe devices when compared to conventional bulk p-MOSFETs at high bias conditions. At low and moderate bias conditions, when surface-roughness does not dominate the carrier transport, we observe performance enhancement in the operation of p-channel SiGe MOSFETs versus their conventional counter-parts.

Germanium: From its discovery to SiGe devices

Germanium, element #32, was discovered in 1886 by Clemens Winkler. Its first broad application was in the form of point contact Schottky diodes for radar reception during WWII. The addition of a closely spaced second contact led to the first all-solid-state electronic amplifier device, the transistor. The relatively low bandgap, the lack of a stable oxide and large surface state densities relegated germanium to the number 2 position behind silicon. The discovery of the lithium drift process, which made possible the formation of p-i-n diodes with fully depletable i-regions several centimeters thick, led germanium to new prominence as the premier gamma-ray detector. The development of ultra-pure germanium yielded highly stable detectors which have remained unsurpassed in their performance. New acceptors and donors were discovered and the electrically active role of hydrogen was clearly established several years before similar findings in silicon. Lightly doped germanium has found applications as far infrared detectors and heavily neutron transmutation doped (NTD) germanium is used in thermistor devices operating at a few milliKelvin. Recently germanium has been rediscovered by the silicon device community because of its superior electron and hole mobility and its ability to induce strains when alloyed with silicon. Germanium is again a mainstream electronic material.

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/ 4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.

Hetero-Interface-Trap Generation due to Hot Carriers in SiGe/Si-Hetero-MOSFETs

It is reported for the first time that hot-carrier-induced degradation occurs in a SiGe/Si heterostructure introduced into the channel region of SiGe/Si-hetero-MOSFETs, using a newly established elaborate low-temperature charge pumping (LTCP) technique. Moreover, the hetero-interface trap density generated and the width of the degraded region are estimated from the LTCP characteristics. These results will enable new levels of improvement to the performance and reliability of strained-Si and SiGe devices.

Si 1 − xGe x sputter epitaxy technique and its application to RTD

A Si 1 − x Ge x sputter epitaxy method using an ultra-high-vacuum-compatible magnetron sputtering technique with an Ar and H 2 mixture working gas has been introduced. The crystallinity and strain-relaxation controllability of a Si 1 − x Ge x layer grown on n-type Si(001) by our sputter epitaxy method is well comparable to those of a Si 1 − x Ge x layer grown by a standard molecular beam epitaxy (MBE) method. In the device level evaluation by forming an electron-tunneling Si/Si 1 − x Ge x asymmetric double quantum well resonant tunneling diode (ASDQW RTD), the fabricated RTD exhibits a high peak-to-valley current ratio (PVCR) of ∼ 26 with low background current, the performance of which is also close to that of our recent high PVCR ASDQW RTD fabricated by gas-source MBE. On the basis of these results, our proposed method is very promising for its application to various kinds of SiGe devices.

Properties of W–Ge–N as a diffusion barrier material for Cu

The properties of W–Ge–N thin films are reported, focusing on issues relevant to their use as diffusion barriers for Cu metallization on silicon. The amorphous W–Ge–N thin films were deposited on thermally grown SiO2∕Si using reactive sputter deposition. This was followed by in situ deposition of Cu films. Annealing studies for W–Ge–N were then carried out in a vacuum to investigate Cu diffusion and barrier film crystallization. X-ray diffraction was used to assess the crystallinity of the films upon annealing. The results show that W–Ge–N has a recrystallization temperature that is higher that that for WNx. Auger electron spectroscopy was used to measure the depth profile of Cu diffusion through the barrier layer. Little or no Cu diffusion was detected for a relatively high annealing temperature. The W–Ge–N films were conductive, although the resistivity is somewhat higher than that for WNx. The results suggest that W–Ge–N may be an attractive diffusion barrier material for Si or SiGe devices.

Voltage stress-induced hot carrier effects on SiGe HBT VCO

This paper presents the hot carrier (HC) induced performance degradation in a 10 GHz voltage controlled oscillator (VCO) with SiGe heterojunction bipolar transistors (HBTs). SiGe device characteristics due to HC stress are examined experimentally. The vertical bipolar inter-company (VBIC) model parameters extracted from measured data are used in Cadence SpectreRF simulation to verify the HC effect on the VCO. The VCO shows significant vulnerability to hot carriers.

Halo implant in pseudomorphic SiGe channel p-MOSFET devices to reduce short channel effect

Halo ion implantation was adopted to reduce the short channel effect (SCE) of a buried channel p-MOSFET device on pseudomorphic Si0.70Ge0.30 layers. The strained pseudomorphic Si0.70Ge0.30 layer of 10 nm thickness, with a Si cap layer on top, was grown using molecular beam epitaxy. The results show an overall reduction in threshold voltage (Vth) roll-off in both Si and pseudomorphic SiGe devices. Halo implantation of As+, 120 keV and dose 2 × 1013 cm−2, was successfully used to reduce roll-off for the 2 nm Si cap SiGe device by 0.3 V. However, it was found that halo implantation causes the reverse short channel effect (RSCE) on the devices, which can result in Vth roll-up with reducing channel length. The effect of the RSCE becomes greater with increasing Si cap thicknesses of the SiGe devices. Also, non-halo implanted devices were found to demonstrate the RSCE. This is due to excess interstitials from the source/drain implant and their subsequent diffusion, which causes virtual halo dopant to form in non-halo implanted devices.