Si FETs Research Articles

IR-OPFET: Infrared Sensor Using PbTiO3 Pyroelectric Film

IR-OPFET having a structure of PbTiO3 thin film gate on Si FET has been fabricated. The pyroelectric property of a tiny PbTiO3 thin film provides a high speed infrared sensitivity with a wide wavelength range at room temperature. A typical performance as an IR-OPFET is that voltage responsivity Rv and detectivity D* are 390 V/W and 3.5×105 cm√Hz/W, respectively, at 20 Hz under infrared irradiation coming through a Ge filter from an incandenscent lamp. The rise time of the response measured by one shot of CO2 laser pulse is estimated to be about 3.5 µsec.

Undissociated Dislocations in Ion Damaged Silicon

Ion implantation in recent years has become an integral part of fabricating electronic devices in Si, e.g., shallow source and drain pockets in FET devices may be fabricated by implanting As+ions at ~ 100 keV to a dose of ~ 1016/cm2. For such implanting conditions, the top layer of the material becomes amorphous and during subsequent heat treatment it grows back epitaxially into a single crystal layer containing dislocations. For several reasons dislocations may be generated in the recrystallized layer. If a high concentration of substitutional species whose atomic radius is sufficiently different from the Si atom radius is incorporated, the strain in this layer may exceed the Si elastic limit and a misfit dislocation network, situated close to the implanted - unimplanted material interface, may form. Certain implanting species may tend to form small clusters with Si atoms and thus causing stacking errors to occur in the growing Si crystal, i.e., dislocations may now be nucleated within the recrystallized layer. However, it is also known that V-shaped dislocation half loops form even for Si+ implanted Si.1 They are apparently nucleated from positions close to the initial amorphous-crystalline Si interface, indicating that certain dislocation nuclei in the crystalline Si beneath the amorphous layer were already generated during implantation. We have presently analyzed the defects in the crystalline material right beneath the amorphous layer by the lattice imaging technique. Among others, the defects of primary interest are undissociated 60° dislocation dipoles of small sizes.

Physical basis of short-channel MESFET operation

MESFETs made of Si, GaAs and InP have been numerically analyzed in two dimensions using the Cornell University Program for Integrated Devices, in order to give physical insight into MESFET operation. Equilibrated electron drift velocity-versus-electric field characteristics and field-dependent anisotropic diffusivities are used in the analysis. Predicted figures of merit, such as cutoff frequency and gate-source capacitance, are compared with experimental results obtained by other authors. Electron transit time, and hence f/SUB T/, in 0.5- and 1.0-/spl mu/m-gate Si, GaAs, and InP FETs is shown to be largely unrelated to the value of low-field mobility in these materials at drain voltages in excess of 1 V. The results relate to the choice of materials for devices in both VLSI digital circuits and microwave linear circuits.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance ( \tau_{d} \sim 100 ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as \tau_{d} = 110 ps).

Physical basis of short-channel MESFET operation

Metal-semiconductor field-effect transistors (MESFET's) made of Si, GaAs, and InP have been numerically analyzed in two dimensions using the Cornell University Program for Integrated Devices (CUPID), in order to give physical insight into MESFET operation. Equilibrated electron drift velocity-versus-electric field characteristics and field-dependent anisotropic diffusivities are used in the analysis. Predicted figures of merit, such as cutoff frequency and gate-source capacitance, are compared with experimental results obtained by other authors. Electron transit time, and hence f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> , in 0.5- and 1.0-µm-gate Si, GaAs, and InP FET's is shown to be largely unrelated to the value of low-field mobility in these materials at drain voltages in excess of 1 V. The results relate to the choice of materials for devices in both VLSI digital circuits and microwave linear circuits.

MA-4 the prospects for ultra-high speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance ( \tau_{d} \sim 100 ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as \tau_{d} = 110 ps).

Excess Noise in Selected Field-Effect Transistors

The origin of excess noise in high-quality FETs is investigated in the frequency domain. It is found that, for use in opto-feedback systems, generation-recombination noise through deep traps is important. It is shown that best initial characterization of transistors for that use can be done in a grounded gate configuration. The activation energy of the principal traps responsible for the g-r noise is calculated and tentative identification of the responsible impurities or defects is made. It is also shown that the basic low temperature limit of Si FET operation is set by majority carrier freeze out at chip temperatures well above 100K and that boron nitride mounts at temperatures above 77K can contribute 10 to 15 eV of 1/f noise.

Fabrication of a miniature 8K-bit memory chip using electron-beam exposure

A fully-ion-implanted miniature 8192-bit random-access memory chip has been fabricated using electron-beam lithography with minimum linewidth between 1 and 1.5 μm and advanced Si FET technology. Device structure, processing steps, mask transfer, and reactive ion etching processes capable of fabricating device structures in the micrometer and submicrometer dimensions are described. With a minimum linewidth of 1.25 μm, the memory chip occupies an area of 1.1×1.6 mm with an array density of 5 million bits/in.2 (0.8 million bits/cm2). A typical readout access time of 90 ns was measured on a functional chip.

Low temperature effects in Si FETs

Low temperature effects in Si FETs