Si-dielectric Interface Research Articles

Angular reflection study to reduce plasmonic losses in the dielectrically displaced back reflectors of silicon solar cells

Metals are an integral part of solar cell structures—as a metal contact and/or a back reflector. However it is a less known fact that there are plasmonic losses associated with these structures and it is important to minimise such losses especially when placed in proximity to scattering media like textures on the front of the cell that can introduce an angular dependence to the light incident on the rear. This study investigates the losses in a metal reflector when placed adjacent to a dielectric layer in a typical solar cell rear geometry. The experimental measurement was realised using a novel custom built optical setup for characterising intensity of the reflected light at various internal incident angles at the Si–dielectric interface. Our results show that the thickness of the dielectric layer, the refractive index of the dielectric layer and the type of the rear metal can all affect the degree of such losses and the distribution of the angular reflection. Both measured and simulation results indicate that a 250–320nm SiO2 along with an Ag back reflector gives the best internal rear angular reflection in Si but is dependant on the wavelength of interest. It also shows that textured or scattering front interfaces with internal incident angles greater than 28° have the potential to provide light trapping through total internal reflection and at the same time minimise plasmonic losses at the metal reflector interface.

Investigation of the Internal Back Reflectance of Rear-Side Dielectric Stacks for c-Si Solar Cells

This paper addresses the calculation of internal back reflectance for various dielectrics that are used in rear-side passivated crystalline silicon solar cells. Optical modeling of various stack configurations is examined to explore the back-surface reflectance at the Si-dielectric interface for different film combinations and thicknesses as a function of wavelength and internal angle of incidence at the rear side. Specifically, configurations using aluminum oxide (AlOx), silicon nitride (SiNx), titanium dioxide (TiO2), and silicon dioxide (SiO2) were investigated with a focus on designing stack configurations that will also allow for high-quality passivation and are compatible with a high-volume manufacturing environment. In addition, samples were fabricated by plasma-enhanced and atmospheric pressure chemical vapor deposition of thin dielectric films onto polished and textured monocrystalline silicon wafers. Spectral reflectance curves of the samples are presented to supplement and validate the conclusions that are obtained from the optical modeling data.

On the Physically Based Compact Gate $C$ –$V$ Model for Ultrathin Gate Dielectric MOS Devices Using the Modified Airy Function Approximation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The exponent <formula formulatype="inline"><tex>$(\lambda)$</tex></formula> of the modified Airy function solution of the quantized energy levels in the MOS potential well, which is used in the physically based quantum-mechanical compact gate <formula formulatype="inline"><tex>$C$</tex></formula>– <formula formulatype="inline"><tex>$V$</tex></formula> model of Li <etal/>, has been found to be dependent on the barrier height at the Si–dielectric interface and the substrate doping density. The physical origins of this dependence are discussed. An empirical equation that considers these effects is proposed for <formula formulatype="inline"><tex>$\lambda$</tex></formula>. Comparison with the experimental <formula formulatype="inline"><tex>$C$</tex></formula>–<formula formulatype="inline"><tex>$V$</tex></formula> data of MOS devices with high-<formula formulatype="inline"><tex>$k$</tex></formula> gate dielectrics shows that inclusion of these effects in the compact <formula formulatype="inline"><tex>$C$</tex></formula>– <formula formulatype="inline"><tex>$V$</tex></formula> model of Li <etal/> is necessary for the accurate simulation of MOS field-effect transistors with high-<formula formulatype="inline"><tex>$k$</tex></formula> gate dielectrics. </para>

Oxygen defects and Fermi level location in metal-hafnium oxide-silicon structures

We describe an in situ method for measuring the band bending of Si substrates in complex metal-oxide-semiconductor systems using femtosecond pump-probe photoelectron spectroscopy. Following deposition of metal layers (Pt, Re, or Re oxide) on the high-k dielectric HfO2, measurement of the band bending in the underlying Si provides a direct determination of the location of the Fermi level within the Si band gap at the Si-dielectric interface. Changes in the Fermi level with post-deposition anneals and oxygen exposure were correlated with valence and core photoelectron spectroscopy as well as capacitance-voltage measurements. These studies illuminate the roles that gate metal work function, modified by metal induced gap states and defects within the oxide, such as oxygen vacancies, play in defining the location of the Fermi level in metal-oxide-semiconductor structures.

A Physically Based Compact Gate&amp;lt;tex&amp;gt;$Chbox--V$&amp;lt;/tex&amp;gt;Model for Ultrathin (EOT&amp;lt;tex&amp;gt;$sim1~hbox nm$&amp;lt;/tex&amp;gt;and Below) Gate Dielectric MOS Devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.

Field-induced reactions of water molecules at Si-dielectric interfaces

ABSTRACTWater molecules and water-related species are present to a varying degree in SiO2 and other dielectrics and at Si-dielectric interfaces. Their presence, even in small concentrations, constitutes a critical reliability problem for present day ultrathin dielectrics. Here we present first-principles density functional calculations that probe the reactivity of water molecules at the Si-dielectric interface. We report results on different possible reaction pathways for water at the interface, including dissociation of water that can lead to the release of H+ ions. The released protons can migrate along the interface and depassivate dangling bonds. Results are also presented for the reaction of water with a hydrogen atom migrating laterally along the interface that lead to the creation of hydronium species. These atomic-scale mechanisms may account for at least some of the creation of interface traps and oxide trapped charge, the two features that give rise to negative bias temperature instability (NBTI), a well known reliability phenomenon that occurs in MOSFETs under normal operating and stress conditions.

Towards a first-principles simulation and current-voltage characteristic of atomistic metal-oxide–semiconductor structures

We describe a theoretical approach to transport and a potentially valuable scheme for screening gate dielectric materials. Realistic structural models of the Si-dielectric interface are employed for $\mathrm{Si}\ensuremath{-}{\mathrm{SiO}}_{2}\ensuremath{-}\mathrm{Si}$ model metal-oxide--semiconductor (MOS) structures. The leakage current for a 1.02-nm MOS structure is calculated from first principles using Landauer's ballistic transport approach and ab inito molecular-dynamic simulation. The calculated leakage currents agree with most recent experimental data.

Plasma processed ultra-thin SiO 2 interfaces for advanced silicon NMOS and PMOS devices: applications to Si-oxide/Si oxynitride, Si-oxide/Si nitride and Si-oxide/transition metal oxide stacked gate dielectrics

The substitution of alternative gate dielectrics for thermally-grown SiO 2 and nitrided SiO 2 in aggressively scaled devices requires a significant processing change in going from thermally-grown to deposited dielectrics. This requires separate and independent steps for (i) the formation of Si-dielectric interface and (ii) the deposition of the dielectric thin film, which can be (a) Si nitride, or a Si oxynitride alloy, or (b) a high- k oxide. It is demonstrated that ultra-thin, nitrided Si–SiO 2 interface layers prepared by 300°C remote plasma processing can be effective in insulating device performance and reliability from deleterious effects associated direct deposition of alternative dielectric materials directly on to hydrogen-terminated Si surfaces. These interfaces perform equally well with Si nitride, Si oxynitride and high- k oxides, and contribute approximately 0.3–0.4 nm to the overall electrical oxide thickness (EOT), limiting aggressive scaling of EOT to approximately 0.6 nm.

Intrinsic limitations on ultimate device performance and reliability at (i) semiconductor–dielectric interfaces and (ii) internal interfaces in stacked dielectrics

The scaling of electrical oxide thickness to 1.0 nm and below for advanced silicon devices requires a change from thermally grown oxides and nitrided oxides to deposited dielectrics which have dielectric constants, k, significantly greater than that of silicon dioxide, k0∼3.8. Implementation of the higher-k dielectrics into field effect transistor devices requires a processing protocol that provides separate and independent control over the properties of the Si–dielectric interface and the bulk dielectric film. Experiments to date have shown that plasma-grown nitrided oxides, ∼0.5–0.6 nm thick, satisfy this requirement. This paper addresses chemical bonding issues at the Si–dielectric interface and at the internal dielectric interface between the plasma-grown nitrided oxides and the high-k alternative dielectrics by applying constraint theory. Si–SiO2 is a prototypical interface between a “rigid” Si substrate and a “floppy” network dielectric, SiO2, and the interfacial properties are modified by a monolayer-scale transition region with excess suboxide bonding over what is required for an ideal interface. Additionally, the defect properties at the internal interface between a nitrided SiO2 interface layer and a bulk dielectric film reflect differences in the average number of bonds/atom, Nav, of the dielectrics on either side of that interface. Experimentally determined interfacial defect concentrations are shown to scale quadratically with increasing differences in Nav thereby establishing a fundamental basis for limitations on device performance and reliability.

Intrinsic limitations on device performance and reliability from bond-constraint induced transition regions at interfaces of stacked dielectrics

The substitution of deposited alternative gate dielectrics for thermally grown SiO2 in aggressively scaled complementary metal–oxide–semiconductor devices requires separate and independent processing steps for (i) the oxidation of the Si substrate to form the Si-dielectric interface and (ii) the deposition of thin film dielectric. Ultrathin plasma-oxidized Si–SiO2 interface layers which contribute approximately 0.3–0.4 nm to the overall electrical oxide thickness have been integrated into devices with Si nitride, Si oxynitride, and Ta2O5 alternative dielectrics. This article proposes an analogy between (i) microscopically inhomogeneous bulk glass alloys such as GeSex with 1&amp;lt;x&amp;lt;2, and (ii) interfaces included in these composite gate dielectric-semiconductor structures including, for examples, the Si–SiO2 and internal dielectric SiO2–Si3N4 interfaces. Scaling relationships for bond defect states applied initially to microscopically inhomogeneous glasses and thin films are applied here to interfaces in stacked gate dielectrics.

The effects of interfacial sub-oxide transition regions and monolayer level nitridation on tunneling currents in silicon devices

Direct tunneling (D-T) in Si metal-oxide-semiconductor (MOS) devices having 1.8 to 3 nm thick gate oxides is reduced approximately tenfold by monolayer Si-dielectric interface nitridation with respect to devices with nonnitrided interfaces. The reduction is independent of gate oxide-equivalent thickness, and gate or substrate injection, and extends into the Fowler-Nordheim tunneling (F-N-T) regime for thicker oxides as well. A barrier layer model, including sub-oxide transition regions, has been developed for the interface electronic structure for tunneling calculations using X-ray photoelectron spectroscopy data. These calculations provide a quantitative explanation for the observed tunneling current reductions.

Silicon oxide/silicon nitride dual-layer films: a stacked gate dielectric for the 21st century

Incorporation of nitrogen atoms into ultra thin (<0.3 nm) gate dielectrics (i) reduces defect generation at the Si–SiO 2 interface, (ii) allows use of physically thicker dielectrics when incorporated into oxide–nitride stacked gate dielectrics, and (iii) prevents boron atom transport out of heavily doped p + polycrystalline silicon gate electrodes when nitrided layers are incorporated at the polycrystalline Si-dielectric interface. I demonstrate that nitrogen atoms can be selectively and independently incorporated into different parts of the gate dielectric structure by low-temperature (∼300°C) remote plasma assisted processing followed by low-thermal budget rapid thermal annealing (RTA) yielding state of the art field effect transistors with oxide equivalent thicknesses less than 2 nm.

Reaction/annealing pathways for forming ultrathin silicon nitride films for composite oxide–nitride gate dielectrics with nitrided crystalline silicon–dielectric interfaces for application in advanced complementary metal–oxide–semiconductor devices

Aggressive scaling of complementary metal–oxide–semiconductor (CMOS) devices requires gate dielectrics with an oxide equivalent thickness, tox,eq∼1 nm or less by the product introduction year 2012. Direct tunneling presents a significant performance limitation in field-effect transistors (FETs) with homogeneous oxide gate dielectrics &amp;lt;1.7 nm. Boron diffusion from p+ poly-Si gate electrodes in p-channel FETs leads to additional electrical problems for oxide thicknesses &amp;lt;3 nm. Interfacial nitridation improves reliability in n-channel FETs; however, by itself, it is not effective in p-type metal–oxide–semiconductor FETs due to boron pileup at the Si–dielectric interface. Proposed solutions include top-oxide surface nitridation and the integration of composite oxide–nitride dielectrics into CMOS devices. This review discusses the integration of hydrogenated silicon nitride films, prepared by remote plasma-enhanced chemical-vapor deposition, into electrical devices with composite oxide–nitride (ON) gate dielectrics. FET devices with ON dielectrics having the same oxide-equivalent thickness, tox-eq and gate dielectric capacitance as devices with homogeneous oxide gate dielectrics display improved performance and reliability. However, reductions in direct tunneling current due to increased physical thickness are below expectations based on tunneling calculations which assume the tunneling mass of electrons in nitride films is approximately the same as in SiO2. The combination of a lower electron tunneling mass and a reduced conduction-band offset energy (i) places important limitations on the extent to which devices with ON gate dielectrics can meet the aggressive scaling needed in advanced CMOS devices, and (ii) raises important questions that have to be addressed when evaluating alternative high-K dielectrics such as Ta2O5, TiO2, and Al2O3. However, tunneling can be reduced by combining monolayer interface nitridation with ON stacks.

Ultrathin nitrided gate dielectrics: Plasma processing, chemical characterization, performance, and reliability

The incorporation of nitrogen (N) atoms into ultrathin gate dielectrics 1) at monolayer levels at Si-SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interfaces reduces tunneling current and defect generation; 2) in bulk nitrides, as in oxide-nitride-oxide (ONO) or oxide-nitride (ON) composite structures, allows the use of physically thicker films without reduced capacitance compared to single-layer oxides; and 3) in nitrided layers at the polycrystalline Si-dielectric interface or in ON dielectrics reduces boron (B) atom out-diffusion from heavily doped p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> polycrystalline silicon gate electrodes into oxide gate dielectrics. The results presented in this review demonstrate that N atoms can be selectively and independently incorporated into different parts of the gate dielectric by low-temperatureremote-plasma-assisted processing. When combined with low-thermal-budget rapid thermal annealing, this yields ultrathin gate dielectrics with performance and reliability which generally exceeds that of single-layer thermally grown oxides. The devices addressed in this paper include n-MOS and p-mos field-effect transistors (FETs) with oxide-equivalent thicknesses of less than 2 nm.