Si Device Layer Research Articles

Enhancing and mapping thermal boundary conductance across bonded Si-SiC interface

SiC is a promising substrate for Si-on-insulator (SOI) wafers for efficient thermal management owing to its high thermal conductivity and large bandgap. However, fabricating a Si device layer on a SiC substrate with a high and uniform thermal-boundary conductance (TBC) at the wafer scale is challenging. In this study, a 4-inch Si-on-SiC wafer was fabricated using a room-temperature surface-activated bonding method, and the TBC was measured using the time-domain thermoreflectance (TDTR) method. The obtained TBC was 109 MW/m2K in the as-bonded sample, improving to 293 MW/m2K after annealing at 750 °C, representing a 78 % increase compared to previously reported values for a Si–SiC interface formed by bonding methods. Such enhancement is attributed to the absence of an oxide layer at the interface. Furthermore, we assessed the actual spatial distribution of the TBC in the SOI system by combining the TDTR mapping with a mathematical model to remove the influence of random errors in the experiment. The spatial distributions before and after annealing were 7 % and 17 %, respectively. Such variation highlights the need to consider the TBC distribution when designing thermal management systems.

Compact light couplers for lateral III-V membrane devices grown on SOI platforms.

Compact light couplers between III-V devices and Si waveguides are crucial for advancing the scalability of Si photonics. Here, we present a compact light coupling strategy for lateral III-V membrane lasers and PDs directly grown on SOI platforms. Benefiting from the coplanar configuration of epitaxial III-V membranes and Si device layer, we designed novel, to our knowledge, butt couplers to achieve both small footprint and high efficiency coupling. We employed sub-wavelength grating structures to gradually bridge the effective refractive index between the III-V membranes and Si waveguide and obtained a coupling loss of less than 0.5 dB across the entire telecom band in a length of less than 10 μm. Our work here offers a fresh perspective for future densely integrated Si photonics.

Comparative Analysis of Surface Characterization Techniques for Atomic Layer Etching

The growing demand for precise atomic level control in device fabrication has led to the rising popularity of Atomic Layer Etching (ALE).1-3 As the name implies, the process facilitates layer-by-layer material removal in an atomic scale, making low surface damage one of the key features of this process. The low-power ion bombardment and the self-limited nature of different process steps help to reduce the damage induced by ALE. However, the damage is not easy to characterize. Atomic Force Microscopy (AFM) is one of the methods that is widely used for surface characterization. However, roughness measurements of the surface using AFM may be misleading as it primarily reflects the top surface, which is typically composed of native oxide rather than the actual Si surface.In this work, we discuss how we used X-Ray reflectometry (XRR) together with ellipsometry to measure the damage induced to the Si device layer of a Silicon on Insulator (SOI) wafer.The experiments were done on an SOI wafer with a 55 nm thick device layer and 145 nm box layer. In order to remove native oxide, all samples were treated with Buffered oxide etch (BOE) 10:1 right before the etch process. The cyclic process was performed in a commercial Inductively Coupled Plasma Reactive Ion Etcher (ICP-RIE) Takachi™ tool from Plasma-Therm LLC, USA. The process gases were Chlorine to activate the Si surface and Ar to remove the activated surface. There was no plasma during activation and purging, it was only ignited during the removal step. XRR, AFM, and ellipsometry characterizations were used to monitor the damage induced by the process. These methods were used to measure the surface roughness before and after the process. In the ellipsometry model, a damage layer is incorporated to evaluate the Si surface that has undergone plasma bombardment resulting in its transformation into amorphous Si. This layer is typically referred to as the surface damage layer. The XRR can measure the roughness on Si layer right beneath the native oxide which again demonstrates the surface damage. On the other hand, AFM measures the roughness at the surface of native oxide.Our results show that while in XRR and ellipsometry, the roughness change follows the same trend, the AFM measurement is not. Results have revealed that in the case of a non-ALE process, both XRR and ellipsometry techniques exhibit a substantial level of surface damage, whereas AFM indicates lower damage. This provides evidence that AFM alone may not be a reliable approach for assessing surface damage. In addition, both XRR and ellipsometry confirm a thick native oxide on top which is very much correlated to the damage. Typically, the thickness of the native oxide is in the ranges between 15-25 Å, and our results support that the thickness of the measured native oxide layer increases with the level of surface damage.

Electrical Characterization of Ultra-Thin Silicon-on-Insulator Films Doped By Means of Phosphorus End-Terminated Polymers

Starting at the 3 nm node, the microelectronics industry is anticipated to transition toward new stacked device architectures, such as gate-all-around field-effect transistors (GAAFETs). In GAAFETs, the gate completely surrounds a silicon nanosheet that serves as a channel, improving the control of the current and performances. The introduction of ultra-scaled stacked 3D devices posed new technological and fundamental problems. In particular, doping techniques commonly used in the mass production of advanced transistors, such as ion implantation or diffusion, present some limitations when applied to these 3D structures. Perego et al.[1] suggested the use of dopant end-terminated polymers as a mild and simple alternative approach to achieve semiconductor doping. Considering the current trend in ultra-scaled microelectronic devices, exploitation of this doping technology requires the demonstration of the possibility to dope thin silicon membranes, achieving a uniform doping concentration throughout the entire film and optimized electrical properties.In this work, ex-situ doping of silicon-on-insulator (SOI) substrates, with device layer thickness ranging from 6 to 70 nm, is performed by using poly(methylmetachrylate) polymers end-terminated with a P containing moiety (PMMA-P), following a procedure described in our previous works.[1,2] Accordingly, a phosphorus δ-layer is created at the interface between a SiO2 capping layer and the underlying Si device layer. Drive-in of the P atoms is performed by annealing the samples in a RTP system at temperatures ranging from 900 to 1200 °C in N2 atmosphere. Annealing time is selected to inject a constant P dose of ∼ 1 x 1013 cm-2 into the SOI substrate, achieving a uniform dopant concentration, as verified by ToF-SIMS measurements. Sample resistivity (ρ), carrier concentration (ne ) and mobility (μ) are determined through sheet resistance and Hall measurements in van der Pauw configuration.Figure 1 shows the results of the electrical and compositional measurements obtained on SOI samples with 30 nm thick device layer as a function of the drive-in temperature. An average activation rate (ηa) above 95% is observed at room temperature in the samples annealed at 1000 °C, indicating full activation of the injected dopants. In the temperature range considered, the mobility is almost constant and is perfectly compatible with values reported in the literature for bulk Si,[3]as shown in the inset. Moreover, the low temperature (5-300 K) electrical characterization indicates that the evolution of ρ, ne and μ values with temperature is consistent with those reported for a P doped bulk Si.[3]Figure 2 shows the results of the electrical and compositional measurements obtained on SOI samples with device layer thickness ranging from 6 to 70 nm upon drive-in of the P dopants at 1000 °C for 100 s. When decreasing the thickness of the device layer, P concentration progressively increases above 1019 atoms/cm3, suggesting that the capping SiO2 film and the buried oxide act as diffusion barrier for P atoms injected into the device layer. ηa well above 80% are achieved for the SOI substrates with device layer thickness greater than 10 nm. However, ηa drops below 10% when further decreasing the thickness of the device layer. A similar reduction of the activation rates was observed in silicon nanowires by Bj ö rk et al.[4]Interestingly, in extremely-thin SOI samples, donor deactivation is correlated to an increase in electron mobility with computed values even greater than those reported for a bulk Si[3], as shown in the inset of Figure 2. Figure 3 shows the relative electron mobility variation as a function of the ratio between the thickness and the average distance between donors for SOI samples annealed at 900 and 1000 °C. The computed values are perfectly compatible with those reported by Kadotani et al.[5] Their model suggests that the enhanced electron mobility observed in heavily doped extremely-thin SOI is caused by the transition from 3D to almost 2D conduction, which results in the reduction of the Coulomb scattering due to the lower number of neighbor donor ions.In conclusion, an experimental study of the doping of ultra-thin SOI by means of phosphorus end-terminated polymers, demonstrates effective doping of silicon with extremely high activation rates of the dopants. Significant deactivation of P atoms and extremely high electron mobility are observed when decreasing the thickness of the device layer below 20 nm where bulk conducting properties transitioned to confinement related phenomena.[1] M.Perego et al., ACS Nano 12 (2018) 178-186.[2] M.Perego et al., J.Mater.Chem.C 8 (2020) 10229-10237.[3] S.M.Sze, K.K.Ng, Physics of Semiconductor Devices (2006) 5-75.[4] M.T.Björk et al., Nature Nanotechnology 4 (2009) 103-107.[5] N.Kadotani et al., Journal of Applied Physics 110 (2011) 034502. Figure 1

Electrical characterization of thin silicon-on-insulator films doped by means of phosphorus end-terminated polymers

Ex-situ doping of 30 nm thick silicon-on-insulator (SOI) substrates is performed by using polymers terminated with a doping containing moiety. Poly(methylmetachrylate) polymers with a P containing moiety are used to create a phosphorus δ-layer at the interface between the Si device layer and a 10 nm thick SiO2 capping layer deposited on the SOI sample by conventional e-beam evaporation. Drive-in of the P atoms is performed by annealing the samples in a rapid thermal processing (RTP) system at temperatures (TA) ranging from 900 to 1200 °C in N2 atmosphere. Annealing time is properly selected to inject a constant P dose of ∼ 1 × 1013 cm−2 into the SOI substrate, achieving a uniform dopant concentration throughout the entire Si device layer as verified by Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) measurements. Sample resistivity (ρ), carrier concentration (ne) and mobility (μ) are determined combining sheet resistance and Hall measurements in the van der Pauw configuration. An average activation rate above 95% is observed at room temperature in the samples annealed at 1000 °C for 100 s, suggesting complete activation of the injected dopants. The detection of phosphorus signal by EPR analysis confirms the extremely high effective concentration of dopants. Low temperature (5–300 K) electrical characterization of a 30 nm thick SOI sample (ne ∼ 2.7 × 1018 cm−3 at 300 K) indicates that the evolution of ρ, ne and μ values as a function of temperature are perfectly consistent, within the experimental error, with those reported for a P doped bulk Si.

A monolithic InP/SOI platform for integrated photonics.

The deployment of photonic integrated circuits (PICs) necessitates an integration platform that is scalable, high-throughput, cost-effective, and power-efficient. Here we present a monolithic InP on SOI platform to synergize the advantages of two mainstream photonic integration platforms: Si photonics and InP photonics. This monolithic InP/SOI platform is realized through the selective growth of both InP sub-micron wires and large dimension InP membranes on industry-standard (001)-oriented silicon-on-insulator (SOI) wafers. The epitaxial InP is in-plane, dislocation-free, site-controlled, intimately positioned with the Si device layer, and placed right on top of the buried oxide layer to form “InP-on-insulator”. These attributes allow for the realization of various photonic functionalities using the epitaxial InP, with efficient light interfacing between the III–V devices and the Si-based waveguides. We exemplify the potential of this InP/SOI platform for integrated photonics through the demonstration of lasers with different cavity designs including subwavelength wires, square cavities, and micro-disks. Our results here mark a critical step forward towards fully-integrated Si-based PICs.

High-performance III-V photodetectors on a monolithic InP/SOI platform

Integrating light emission and detection functionalities using efficient III-V materials on Si wafers is highly desirable for Si-based photonic integrated circuits. To fulfill the need of high-performance photodetectors (PDs) monolithically integrated on Si for Si photonics, we demonstrate III-V PDs directly grown on a InP/Si-on-insulator (SOI) platform parallel to the Si device layer in a variety of device dimensions. Device characteristics including a 3 dB bandwidth beyond 40 GHz, open eye diagrams at 40 Gb/s, a dark current of 0.55 nA, a responsivity of 0.3 A/W at 1550 nm, and 0.8 A/W at 1310 nm together with a 410 nm operation wavelength span from 1240 nm to 1650 nm are achieved. We further simulate the feasibility of interfacing the III-V PDs with the Si waveguide by designing waveguide-coupled PDs with butt coupling schemes. These results point to a practical solution for the monolithic integration of III-V active components and Si-based passive devices on a InP/SOI platform in the future.

High-Overtone Thin Film Ferroelectric AlScN-on-Silicon Composite Resonators

This letter presents the first demonstration of thin-film ferroelectric Aluminum Scandium Nitride (AlScN)-on-silicon composite resonators, targeting high-overtone resonance modes in the sub-6GHz band with a high figure of merit (FoM). The resonators are based on sputtered ferroelectric AlScN films with Sc/(Al+Sc) ratio of ~30% and thickness of $\sim 1 {\mu }\text{m}$ . Two types of AlScN thickness-extensional (TE) resonators are co-fabricated on the same SOI platform; with and without a $3.55~\mu \text{m}$ -thick Si layer in the resonant stack. We show that although the passive Si device layer underneath the thin piezo-stack results in degradation of the electromechanical coupling coefficient $({k}_{t}^{2})$ , it boosts the quality factor $({Q})$ , provides structural robustness, and improves the overall ${Q} \times {k}_{t}^{2}$ FoM. The resonant frequency spectrum of the high-overtone TE modes of AlScN-on-Si composite resonator is analyzed and the dependency of ${k}_{t}^{2}$ on the Si device layer properties is studied. A high ${k}_{t}^{2}$ value of 11.7% at the 3rd-order TE resonant frequency of 2.4 GHz is reported, yielding a high ${k}_{t}^{2}\times {Q}_{\textit {max}}$ FoM of 84. The reported FoM shows $2\,\, {\times }$ improvement compared to the co-fabricated AlScN-only FBARs.

Epitaxial Nanostructured α-Quartz Films on Silicon: From the Material to New Devices.

In this work, we show a detailed engineering route of the first piezoelectric nanostructured epitaxial quartz-based microcantilever. We will explain all the steps in the process starting from the material to the device fabrication. The epitaxial growth of α-quartz film on SOI (100) substrate starts with the preparation of a strontium doped silica sol-gel and continues with the deposition of this gel into the SOI substrate in a thin film form using the dip-coating technique under atmospheric conditions at room temperature. Before crystallization of the gel film, nanostructuration is performed onto the film surface by nanoimprint lithography (NIL). Epitaxial film growth is reached at 1000 °C, inducing a perfect crystallization of the patterned gel film. Fabrication of quartz crystal cantilever devices is a four-step process based on microfabrication techniques. The process starts with shaping the quartz surface, and then metal deposition for electrodes follows it. After removing the silicone, the cantilever is released from SOI substrate eliminating SiO2 between silicon and quartz. The device performance is analyzed by non-contact laser vibrometer (LDV) and atomic force microscopy (AFM). Among the different cantilever's dimensions included in the fabricated chip, the nanostructured cantilever analyzed in this work exhibited a dimension of 40 µm large and 100 µm long and was fabricated with a 600 nm thick patterned quartz layer (nanopillar diameter and separation distance of 400 nm and 1 µm, respectively) epitaxially grown on a 2 µm thick Si device layer. Themeasuredresonance frequency was267 kHz and the estimated quality factor, Q, of the whole mechanical structure was Q ~ 398 under low vacuum conditions. We observed the voltage-dependent linear displacement of cantilever with both techniques (i.e., AFM contact measurement and LDV). Therefore, proving that these devices can be activated through the indirect piezoelectric effect.

Development and co-integration of a SMA/Si bimorph nanoactuator for Si photonic circuits

This paper presents a novel design and fabrication process for co-integration of SMA/Si bimorph nanoactuators with footprint of 10 μm2 into silicon waveguide structures to enable ultra-compact optical waveguide switching. The nanoactuator is directly attached to a free-standing waveguide being part of a directional coupler. The design includes an etch window for local sacrificial layer processing below the nanoactuator and free-standing monomode waveguides. 3D finite element simulations are performed to evaluate actuator deflection-dependent coupling efficiencies. Fabrication comprises three-step e-beam lithography on a SOI wafer, cryo etching of the Si device layer and magnetron sputtering of the SMA layer. First demonstrators reveal actuator deflections up to 1 μm with reproducibility in the order of 4 nm.

Bufferless 1.5 µm III-V lasers grown on Si-photonics 220 nm silicon-on-insulator platforms

Efficient III-V lasers directly grown on Si remain the “holy grail” for present Si-photonics research. In particular, a bufferless III-V laser grown on the Si-photonics 220 nm silicon-on-insulator (SOI) platform could seamlessly bridge the active III-V light sources with the passive Si-based photonic devices. Here we report on the direct growth of bufferless 1.5 µm III-V lasers on industry-standard 220 nm SOI platforms using metal organic chemical vapor deposition (MOCVD). Taking advantage of the constituent diffusivity at elevated growth temperatures, we first devised a MOCVD growth scheme for the direct hetero-epitaxy of high-quality III-V alloys on the 220 nm SOI wafers through synergizing the conventional aspect ratio trapping (ART) and the lateral ART methods. In contrast to prevalent epitaxy inside V-grooved pockets, our method features epitaxy inside trapezoidal troughs and thus enables the flexible integration of different III-V compounds on SOIs with different Si device layer thicknesses. Then, using InP as an example, we detailed the growth process and performed extensive study of the crystalline quality of the epitaxial III-V. Finally, we designed and fabricated both pure InP and InP/InGaAs lasers, and we achieved room-temperature lasing in both the 900 nm band and the 1500 nm band under pulsed optical excitation. Direct epitaxy of these in-plane and bufferless 1.5 µm III-V lasers on the 220 nm SOI platform suggests the imminent interfacing with Si-based photonic devices and the subsequent realization of fully integrated Si-based photonic circuits.

Thin-Piezo on Single-Crystal Silicon Reactive Etched RF MEMS Resonators

This paper demonstrates how a single crystal silicon wafer can be used to fabricate thin-film piezoelectric-on-silicon (TPoS) resonators by utilizing a modified version of Single Crystal Silicon Reactive Etch and Metallization (SCREAM) process. The developed process enables the fabrication of MEMS resonators with varied device layer thicknesses ranging from sub-micrometer to tens of micrometers (one thickness per die) from a single bulk silicon wafer, while avoiding the need of costly silicon-on-insulator (SOI) substrates. The thin-film piezoelectric on single-crystal silicon reactive etched technique allows batch fabrication of TPoS resonators, while also retaining the same number of photolithography steps. To maintain a good resonator body sidewall roughness, a conformal Al2O3 thin film was deposited by atomic layer deposition to act as the sidewall protection layer. Through the developed process, resonators with varied silicon layer ranging from $0.1~\mu \text{m}$ to $47~\mu \text{m}$ have been successfully implemented. The measured results under different ZnO-to-Si thickness ratios have been studied, in terms of motional impedance ( $R_{\mathrm {m}}$ ), quality factor ( $Q$ ), and resonance frequency. It is noted that TPoS MEMS resonators operating in fundamental and higher lateral extensional modes exhibit their best performance under an optimal ZnO-to-Si thickness ratio. Resonators fabricated by the modified TPoS process with a Si device layer thickness of 4- $20~\mu \text{m}$ exhibits optimal performance. The highest $Q$ of 1,567 for a disk resonator and the lowest motional impedance of 791 $\Omega $ for a square plate resonator were achieved with Si layer thicknesses of $20~\mu \text{m}$ and $4~\mu \text{m}$ , respectively.

Selective lateral epitaxy of dislocation-free InP on silicon-on-insulator

Efficient on-chip laser sources of Si photonics can be built from direct epitaxy of dislocation-free III–V alloys on industrial-standard (001) Si wafers. Here, we report on selective lateral epitaxy of InP on patterned (001) silicon-on-insulators (SOIs) by metal organic chemical vapor deposition. Based on the conventional “aspect ratio trapping” approach, we created undercut patterns to alter the growth front to the lateral direction. Growth of InP inside the nano-scale SOI trenches results in dislocation-free InP crystals right atop the buried oxide layer. The intimate placement of the InP crystals with the Si device layer points to the development of dislocation-free nano-ridges for integration of efficient III–V light emitters with Si-based photonic components on SOI.

Planar Junctionless Silicon-on-Insulator Transistor With Buried Metal Layer

In this letter, we propose a novel structure of an n-channel silicon-on-insulator junctionless transistor (SOI-JLT) with improved ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio and scalability. A buried metal layer (BML) of appropriate workfunction ( $\phi _{\text {BM}}$ ) is used to create a Schottky junction at the bottom of Si device layer, whereas the source–channel–drain path is junctionless and hence named the buried-metal-SOI-lateral JLT (BM-SOI-LJLT). The BML-induced bottom depletion layer combined with the depletion region due to top gate results in a perfect volume depletion in OFF state. A 2-D calibrated simulation has shown an ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ~108 in BM-SOI-LJLT compared to ~2 in the conventional SOI-JLT at $\phi _{\text {BM}}$ of 5.1 eV and a gate length of 20 nm. Furthermore, the lateral band-to-band tunneling parasitic leakage is significantly lower in the BM-SOI-LJLT and does not degrade its ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio. Furthermore, high vertical field due to the Schottky junction minimizes the lateral coupling between the source and drain field lines and thus improves the short-channel-effect suppression and scalability of the proposed device.

Tailoring the quality factors and nonlinear response in hybrid plasmonic-dielectric metasurfaces.

Plasmonic nanoantennas and metamaterials concentrate optical energy into nanometric volumes strongly enhancing the light-matter interaction. This makes them promising platforms for optical sensing, nonlinear effects and quantum optics. However, absorption losses and radiative damping result in broad, low quality factor (Q) resonances of plasmonic systems that significantly limit their performance. Here, we develop a hybrid plasmonic/dielectric metasurface that can simultaneously achieve high Q and large field enhancement values in the near infrared by forming a hybridized mode between the nanoantennas' plasmonic mode and the photonic waveguide mode of Si device layer. The tunability of the modes and quality factors of our platform allows us to study the effect of the geometric parameters on the optical properties of the metasurface. We demonstrate that the strongest near field enhancement and nonlinear signal generation can be achieved by balancing the high Q factors and in-coupling efficiency in hybrid resonators.

The Effect of Interfacial Charge on the Development of Wafer Bonded Silicon-on-Silicon-Carbide Power Devices

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer.

Fabricating with crystalline Si to improve superconducting detector performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Study of the effect of thermal treatment on morphology and chemical composition of silicon-on-insulator

Removing the ultrathin native oxide layer from silicon-on-insulator (SOI) without damaging the Si device layer poses several processing challenges, the main one being the maintenance of the device layer integrity during oxide layer removal. In order to address this challenge and find a low thermal budget process, the thermal decomposition of the ultrathin native oxide in ultrahigh vacuum has been investigated using scanning electron microscopy, atomic force microscopy, scanning tunneling microscopy, and x-ray photoelectron spectroscopy. The evolving morphology and chemical composition of the ultrathin oxide and the SOI device layer were investigated as a function of anneal temperature and duration. Multiple anneal cycles at 750 °C, each lasting for 30–90 s, was found to be an effective method of desorbing the oxide without causing dewetting of the device layer. The total amount of carbon present on the sample was not altered significantly by thermal treatment; however, a change in the chemical composition of the carbon was noted. A simple oxygen plasma-based ex situ cleaning step before annealing was found to be effective in reducing the density of SiC on the annealed sample while keeping the annealed surface atomically smooth.

High quality extremely thin SOI fabricated by facilitated ion-cut with H-trapping effect

High-quality strain-relaxed extremely thin silicon-on-insulator (ETSOI) has been fabricated by using H-trapping and etch-stop process in the H-implanted Si/Si0.70Ge0.30/Si/B-doped Si0.70Ge0.30/Si heterostructure. Compared to conventional ion-cut process, the combination of ultrathin SiGe interlayer with boron doping can significantly decrease the critical hydrogen implantation dosage needed for layer transfer by improving H-trapping efficiency. During subsequent annealing process, implanted H preferentially agglomerates at the trapping centers and induces long microcracks at the B-doped Si0.70Ge0.30/Si interface as well as in the near-interface region. The selective etch-stop process was used to remove residual Si/SiGe layers to expose a strain-relaxed Si device layer with a smooth surface morphology. These results demonstrate facilitated ion-cut as a promising approach for fabricating high crystalline quality ETSOI substrate and further offer a potential solution for scaling planar complementary metal–oxide–semiconductor to 22 nm node and beyond.

Development of Silicon Probe With Acute Study on <italic>In Vivo</italic> Neural Recording and Implantation Behavior Monitored by Integrated Si-Nanowire Strain Sensors

The silicon probe with highly P-doped Si electrodes was realized on 8-in Silicon on insulator wafer through standard Complementary metal-oxide semiconductor process. By leveraging the same thin Si device layer ( $\sim 100$ nm), the built-in piezoresistive Si-nanowires (SiNWs) configured in full-bridge structure were also equipped along the probe shank for strain sensing. After additional coatings of nanocomposite (Carbon nanotubes + Au nanoparticles) on silicon electrodes, the functionality of neural recording was validated with a low noise level ( $ ) during in vivo neural recording on rat brain (CA1 region). The additional capability of monitoring probe mechanical behavior was first verified through the probe buckling experiments and further examined with implantations on rat brain (S1 region). Besides the large buckling mechanics, the physiological brain micromotion (e.g., caused by respiration) was successfully picked up by integrated SiNWs strain sensors, which would provide the research platform to practically understand the correlation between the electrical neural signal and the brain micromotion. [2014-0370]