Shuffle Network Research Articles

Multistage shuffle networks with shortest path and deflection routing for high performance ATM switching: the open-loop shuffleout

Multistage shuffle networks with shortest path and deflection routing for high performance ATM switching: the open-loop shuffleout

A general performance analysis method for uniform memory architectures

The performance of a multiprocessor system greatly depends on the bandwidth of its memory architecture. In this paper, uniform memory architectures with various interconnection networks including crossbar, multiple-buses and generalized shuffle networks are studied. We propose a general method based on the Markov chain model by assuming that the blocked memory requests will be redistributed to the memory modules in the next memory cycle. This assumption results in an analysis with lower complexity where the number of states is linearly proportional to the number of processors. Moreover, it can provide excellent estimation on the system power and memory bandwidth for all three types of interconnection networks as compared with the simulation results in which the blocked memory requests are resubmitted to the same memory module. Comparisons also show that our method is more general and precise than most existing analysis methods. The method is further extended to estimate the performance of multiprocessor system with caches. The approximation results are also shown to be remarkably good.

A complexity analysis of smart pixel switching nodes for photonic extended generalized shuffle switching networks

The architectural tradeoffs found in the use of smart pixels for nodes within photonic switching interconnection networks are discussed. The particular networks of interest within the analysis are strictly nonblocking extended generalized shuffle (EGS) networks. Several performance metrics are defined for the analysis, and the effect of node size on these metrics is studied. Optimum node sizes are defined for each of the performance metrics and system-level limitations are identified.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Free-space photonic switching architectures based on extended generalized shuffle networks

A new class of networks that is well suited for free-space photonic switching applications is described. These networks are known as extended generalized shuffle networks. It is shown that these networks can provide low blocking probabilities while requiring low hardware costs. In fact, if sufficient hardware is added to these networks, they become strictly nonblocking networks (with blocking probabilities equal to zero). The hardware cost of an extended generalized shuffle network can be modified to yield any desired blocking probability, so cost-effective designs are possible. In addition, it is shown that these networks are extremely fault tolerant, and they can also be designed to have high system availabilities. Because the networks can use various types of interconnections to connect the nodes and because the nodes can have various types of functionality, these networks also provide high degrees of flexibility that can be used to optimize a free-space photonic design. The design of extended generalized shuffle networks based on a particular node type that is easy to implement with symmetric self-electro-opticeffect devices is studied.

2-D SIMD algorithms for perfect shuffle networks

In this paper we study a set of basic algorithms for SIMD Perfect Shuffle networks. These algorithms were studied in the works of Schwartz ( ACM TOPLAS 2 (1980) , 484–521) and Nassimi and Sahni ( IEEE Trans. Comput. C 30, 2 (Feb. 1981) , 101–107), for the 1-D case, where the size of the problem N is the same as the number of processors P. For the 2-D case of N = L ∗ P, studied also by Gottlieb and Kruskal (Ultracomputer Note No. 11) and Kruskal (Ph.D. dissertation, Courant Institute, New York University, 1981), we improve the run time of several algorithms. In particular, the run time of Row Reduction and Parallel Prefix is improved from O(L ∗ P) to O( L + log P). An adaptive method for gathering global information is introduced, implying a fast algorithm for Smoothing (off-line load balancing). Optimal algorithms for Cartesian Product and for the Transpose operations are devised. Other problems, important variants of these problems, and lowerbounds can be found in the work of Ben-Asher, Egozi, Schuster (Hebrew University Tech. Rep. 88-14, Oct. 1988).

Photonic switching nodes based on self electro-optic effect devices

Photonic switching nodes based on self electro-optic devices are described. These nodes are proposed for use in extended generalized shuffle networks with free space digital optical interconnections between nodes. Several experiments are described demonstrating both individual switching nodes and arrays of switching nodes operating concurrently. Node complexity, optical system complexity, and tolerance issues associated with different types of nodes are also discussed.

Optically efficient free-space folded perfect shuffle network

A light-efficient folded perfect shuffle network is described. Two-dimensional (2-D) raster encoding of the processing element nodes is used to accommodate large arrays with simple imaging optics. The network uses 2-D arrays of lenslets and prisms to correct for magnification and replication losses. Simulation results show the required prism arrays to be of low complexity and suggest that the network is tolerant to imperfections in the prism parameters.

Embedding shuffle networks in hypercubes

We consider the problem of embedding perfect shuffle and shuffle exchange networks in hypercubes. We prove that perfect embedding is possible for perfect shuffle with 2 k nodes only when k is a power of 2, and we give an efficient algorithm for embedding perfect shuffle networks with 2 k nodes when k is a power of 2. We also discuss a scheme for embedding shuffle exchange networks with 2 k nodes, k being a power of 2, and give its extensions to the general case.

A selective-broadcast passive star coupler for self-routing dense wavelength division multiplexed optical networks

The authors describe a technique for design and implementation of a selective-broadcast passive optical star coupler, that uses a space-varying refractive-index slab. A network traffic routing matrix can be incorporated in the design fabric of this bandwidth-selective coupler. The matrix may resemble any desired physical cross connection for routing user traffic. As an example, the authors show how a perfect shuffle network connectivity can be built into the fabric of a passive star coupler. A wave-mixing method is proposed to configure such a coupler. With this implementation, the authors have realized the physical connectivity appropriate for any desired routing matrix in dense wavelength division multiplexed optical star network applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New FFT structures based on the Bruun algorithm

In some signal processing applications, the input data are real. In this case, the Bruun algorithm for computation of the discrete Fourier transform (DFT) is attractive. The author offers a pipeline and a recirculated shuffle network implementation of the Bruun algorithm. The implementation of the parallel pipeline and recirculated FFT structures is based on the modified perfect shuffle network.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

2-D SIMD algorithms in the perfect shuffle networks

This paper studies a set of basic algorithms for SIMD Perfect Shuffle networks. These algorithms where studied in several papers, but for the 1-D case, where the size of the problem N is the same as the number of processors P . For the 2-D case of N = L * P , studied by [GK-80] and [Kr-81], we improve several algorithms, achieving run time Ο( L + log P ) rather than Ο( L * log P ), as N exceeds P . We give non-trivial algorithms for the following 2-D operations: Row-Reduction, Parallel-Prefix, Transpose, Smoothing and Cartesian-Product.

Image processing on a transputer-based perfect shuffle machine

This paper describes a transputer-based parallel MIMD computer and its application to image processing. The computer consists of a one-dimensional array of processing nodes with nearest neighbour connections and an additional perfect shuffle network. Several examples demonstrate that this machine can efficiently solve the typical computational tasks of low and medium level image processing.

An analysis of cube-connected cycles and circular shuffle networks for parallel computation

This paper is concerned with demonstrating isomorphism between two classes of computer architectures that support parallel computation, viz., the cube-connected cycles (CCC) network and the homogeneous circular shuffle network (HCSN). This is done by developing a suitable and common notation for addressing processing elements and specifying interconnections in the two networks. The implications of such an equivalence are discussed. Properties and algorithms concerning HCSN networks, with respect to routing and fault tolerance, thereby, immediately become applicable to CCC networks. As for HCSN networks, their VLSI layout is now apparent. The networks are shown to be totally symmetric with respect to each processor, and in some cases may be recursively defined in terms of modules. Further, any algorithm that runs on an HCSN network also runs on a CCC network without any modification. It is also shown that a large class of algorithms that run on a CCC network can be implemented, with slight modification, on an HCSN network. In particular, an implementation of the DESCENT algorithm on an HCSN network is proposed.

Solving Tridiagonal Systems on Ensemble Architectures

The concurrent solution of tridiagonal systems on linear and 2-dimensional arrays, complete binary trees, shuffle-exchange and perfect shuffle networks, and boolean cubes by elimination methods are devised and analyzed. The methods can be obtained by symmetric permutations of some rows and columns, and amounts to cyclic reduction or a combination of Gaussian elimination and cyclic reduction (GECR). The ensembles have only local storage and no global control. Synchronization is accomplished via message passing to neighboring processors.The parallel arithmetic complexity of GECR for N equations on a K processor ensemble is $O({ N / K } + \log _2 K)$, and the communication complexity is $O(K)$ for the linear array, $O(\sqrt K )$ for the 2-dimensional mesh, and $O(\log _2 K)$ for the networks of diameter $O(\log _2 K)$. The maximum speed-up for the linear array is attained at $K \approx {({ N / \alpha })}^{1/2} $ and for the 2-d mesh at $K \approx ({N / 2\alpha })^{2/3} $, where $\alpha $ (the time to communicate one floating-point number)/(the time for a floating-point arithmetic operation). For the binary tree the maximum speed-up is attained at $K = N$, and for the perfect shuffle and boolean k-cube networks, $K = N/(1 + \alpha )$ yields the maximum speed-up. The minimum time complexity is of order $O(N^{1/2} )$ for the linear array, of order $O(N^{1/3} )$ for the mesh, and of order $O(\log _2 N)$ for the binary tree, the shuffle-exchange, the perfect shuffle and the boolean k-cube.The relative decrease in computational complexity due to a truncation of the reduction process in a highly concurrent system is much greater than on a uniprocessor. The reduction in the arithmetic complexity is proportional to the number of steps avoided, if the number of processing elements equals the number of equations. So also is the reduction in the communication complexity for ensembles configured as binary trees, shuffle-exchange and perfect shuffle networks, and boolean cubes.Partitioning the ensemble into subsets of processors is shown to be more efficient for the solution of multiple independent problems than pipelining the solutions over the entire ensemble. A balanced cyclic reduction algorithm is presented for the case where each system is spread uniformly over the processing elements, and its complexity is compared with Gaussian elimination.

A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture

The paper describes a multistage shuffle interconnection network which is controlled by a central monitor. A control code broadcast by the monitor to all the basic switching elements of the network simultaneously, makes the network dynamically reconfigurable. The control code plays three vital roles. Firstly, it establishes conflict-free paths between several source-destination pairs. Thus the problem of collision, a major obstacle of a self-routing network, is completely eliminated. Secondly, the direct paths are established in one clock period irrespective of the number of stages. This makes the system faster. Thirdly, the control code also acts as a grouping code for executing a table of arbitrary data exchange requests between nodes in minimum number of passes. It is also shown that the network can be made fault-tolerant by the addition of an extra stage. Any single fault and some multiple faults in the intermediate stages can be tolerated by this scheme. Moreover, the switching from the faulty state to the fault-free state can be done in a single clock period, thus enabling fast fault-tolerant reconfiguration.

Design and Performance of Generalized Interconnection Networks

This paper introduces a general class of self-routing interconnection networks for tightly coupled multiprocessor systems. The proposed network, named a "generalized shuffle network (GSN)," is based on a new interconnection pattern called a generalized shuffle and is capable of connecting any number of processors M to any number of memory modules N. The technique results in a variety of interconnection networks depending on how M nd N are factored. The network covers a broad spectrum of interconnections, starting from shared bus to crossbar switches and also includes various multistage interconnection networks (MIN's).

Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees

In this paper we describe two interconnection networks for parallel processing, namely the orthogonal trees network and the orthogonal tree cycles (OTN and OTC). Both networks are suitable for VISI implementation and have been analyzed using Thompson's model of VLSI. While the OTN and OTC have time performances similar to fast networks such as the perfect shuffle network (PSN), the cube comnected cycles (CCC), etc., they have substantially better area * time2 performances for a number of matrix and graph problems. For instance, the connected components and a minimal spanning tree of an undirected N-vertex graph can be found in 0(log4 N) time on the OTC with an area * time2 performance of 0(N2 log8 N) and 0(N2 log9 N) respectively. This is asymptoticaly much better than the performances of the CCC, PSN and Mesh. The OTC and OTN can be looked upon as general purpose parallel processors since a number of other problems such as sorting and DFT can be solved on them with an area * time2 performance matching that of other networks. Finally, programming the OTN and OTC is simple and they are also amenable to pipelining a series of problems.