Shortest Linear Feedback Shift Register Research Articles

Exploring the parallel capabilities of GPU: Berlekamp-Massey algorithm case study

Graphics processors Unit (GPU) architectures are becoming increasingly programmable, offering the potential for dramatic speedups for a variety of general purpose applications compared to contemporary general- purpose processors (CPUs). However, there are several optimization techniques which are used to maximize the benefit of the GPU resources. This research exploits optimization techniques for CUDA enabled GPU architecture in order to achieve the best possible performance for Berlekamp-Massey Algorithm (BMA) as a case study. Berlekamp-Massey Algorithm (BMA) is one of the best solutions to find the shortest linear feedback shift register which is very important for several applications such as digital processing and cryptography. The experimental results show that the optimized BMA implementation is almost 160 × faster than non-bit CPU serial implementation, 7 × faster than bit serial implementation and 4 × faster than an initial parallel bit implementation.

Linear feedback shift registers and the minimal realization problem

The Berlekamp–Massey algorithm solves the problem of finding the shortest linear feedback shift register which generates a given finite sequence of scalars. This problem is reinterpreted from the point of view of the realization theory and several extensions to sequences of matrices are analyzed. We give a generalization of the result on which the Berlekamp–Massey algorithm is based in terms of the partial Brunovsky indices of a sequence of matrices and propose an algorithm to obtain them for sequences of vectors. The results we obtain hold for arbitrary fields.

Parallel SIMD CPU and GPU Implementations of Berlekamp–Massey Algorithm and Its Error Correction Application

The Berlekamp–Massey algorithm finds the shortest linear feedback shift register for a binary input sequence. A wide range of applications like cryptography and digital signal processing use this algorithm. This research proposes novel parallel mechanisms offered by heterogeneous CPU and GPU hardwares in order to achieve the best possible performance for BMA. The proposed bitwise implementation of the BMA algorithm is almost 35 times faster than state of the art implementations. This further improvement is achieved by using SIMD instructions which provides data level parallelism. This new approach can be 4.6 and 35 times faster than a bitwise CPU and state of the art implementations, respectively. In order to achieve the highest possible speedup over a multi-core structure, a multi-threading implementation is introduced in this research. By leveraging on OpenMP we were able to obtain a speedup of 10 times over 12 cores server. The GPU device with thousands of processing cores can bring great speedup over the best CPU implementation. Two other parallel mechanisms offered by GPU are concurrent kernel execution and streaming. They achieve 14.5 and 2.2 times of speedup compared to CPU serial and typical CUDA implementations, respectively. Also, the performance of the openMP code with SIMD instructions is compared with GPU stream implementation. The effectiveness of the proposed method is evaluated in a real world error correction application and it achieves 6.8 times of speedup.

A New Architecture of Test Response Analyzer Based on the Berlekamp–Massey Algorithm for BIST

Lately, built-in self-test (BIST) has been of great importance in the manufacture of very large scale integration (VLSI) circuits. Most BIST schemes compress the test response into a compact signature using space and/or time compaction. A fundamental problem associated with response compaction is error masking or aliasing. In this paper, an alternative zero-aliasing test response evaluation scheme for BIST is presented. The main conceptual ingredient utilized to build the proposed scheme is the application of the Berlekamp-Massey algorithm (BMA). The BMA provides a general solution for synthesizing the shortest linear feedback shift register (LFSR) capable of generating a given finite sequence. Basically, on the BIST design stage and considering the fault-free test response sequence, the BMA is used to synthesize an LFSR capable of generating this sequence in an economical way. The BIST testing stage consists in comparing the obtained test response sequence of the circuit under test (CUT) with the fault-free test response sequence generated by the LFSR previously designed. This way, a testing of the CUT can be made. It is observed that there is no aliasing using the proposed scheme. The key to make this scheme attractive is to keep the LFSR length as small as possible. Based on it, two derived schemes, called Simple-LFSR and Multi-LFSR, are shown to try to solve this problem. Experimental results are shown for some ISCAS85 benchmarks.

Linear complexity of modulo-m related prime sequences

The linear complexity of m-phase related prime sequences is investigated for the case when m is composite. For each relatively prime factor pik of m, the linear complexity and the characteristic polynomial of the shortest linear feedback shift register that generates the pik-phase version of the sequence can be deduced and these results can then be combined using the Chinese remainder theorem to derive the m-phase values. These values are shown to depend on the categories of the sequence length computed modulo each factor of m, rather than on the category of the length modulo m itself, and that these values depend on the primitive roots employed. For a given length, the highest values of linear complexity result from constructing the sequences using those values of primitive elements that lead to non-zero categories for each factor of m.

Linear complexity of modulo-m power residue sequences

The linear complexity of m-phase power residue sequences is investigated for the case when m is composite. For each factor of m, the linear complexity and the characteristic polynomial of the shortest linear feedback shift register that generates this version of the sequence can be deduced and these results can then be combined using the Chinese remainder theorem to derive the m-phase values. These values are shown to depend on the categories of the length of the sequence computed modulo of each factor of m, rather than on the category of the length modulo-m itself. For a given length, the highest values of linear complexity results from constructing the sequences using those values of the primitive element which lead to non-zero categories for each factor of m.

On the linear complexity of Legendre sequences

We determine the linear complexity of all Legendre sequences and the (monic) feedback polynomial of the shortest linear feedback shift register that generates such a Legendre sequence. The result shows that Legendre sequences are quite good from the linear complexity viewpoint.

On Multisequence Shift Register Synthesis and Generalized-Minimum-Distance Decoding of Reed-Solomon Codes

In this paper, it is shown that the problem of generalized-minimum-distance (GMD) decoding of Reed-Solomon (RS) codes can be reduced to the problem of multisequence shift register synthesis, and a simple algorithm is presented that yields a solution for this problem by finding, for k = 1, 2, . , the shortest linear feedback shift register that can generate each of the first k sequences of a special kind of multisequence. The algorithm is based on the well-known Berlekamp-Massey algorithm for a single-sequence problem and is only a little more complex than it. Also presented is a GMD decoding algorithm for RS codes which employs the proposed multisequence shift register synthesis algorithm and whose complexity is less than 3 nd + 8 d 2 for the code length n and the minimum distance d. This GMD decoding algorithm provides an alternative to algorithms based on the Welch-Berlekamp algorithm.

On evaluating the linear complexity of a sequence of least period 2 n

The linear complexity of a periodic binary sequence is the length of the shortest linear feedback shift register that can be used to generate that sequence. When the sequence has least period 2 n ,n≥0, there is a fast algorithm due to Games and Chan that evaluates this linear complexity. In this paper a related algorithm is presented that obtains the linear complexity of the sequence requiring, on average for sequences of period 2 n ,n≥0, no more than 2 parity checks sums.

A generalization of the Berlekamp-Massey algorithm for multisequence shift-register synthesis with applications to decoding cyclic codes

A generalization of the Berlekamp-Massey algorithm is presented for synthesizing minimum length linear feedback shift registers for generating prescribed multiple sequences. A more general problem is first considered, that of finding the smallest initial set of linearly dependent columns in a matrix over an arbitrary field, which includes the multisequence problem as a special case. A simple iterative algorithm, the fundamental iterative algorithm (FIA), is presented for solving this problem. The generalized algorithm is then derived through a refinement of the FIA. Application of this generalized algorithm to decoding cyclic codes up to the Hartmann-Tzeng (HT) bound and Roos bound making use of multiple syndrome sequences is considered. Conditions for guaranteeing that the connection polynomial of the shortest linear feedback shift register obtained by the algorithm will be the error-locator polynomial are determined with respect to decoding up to the HT bound and special cases of the Roos bound. >

The complexity of a periodic sequence over GF( p)

Some algorithms for finding the complexity and the connection polynomial of the shortest linear feedback shift register that generates a periodic sequence over GF( p) are proposed.

A simple derivation of the Berlekamp- Massey algorithm and some applications (Corresp.)

Another viewpoint is presented on the derivation of the Berlekamp-Massey algorithm. Our approach differs from previous ones in the following manner. The properties of the shortest linear feedback shift register that generates a given sequence are first derived Without reference to the Berlekamp-Massey algorithm. The Berlekamp-Massey algorithm is then derived using these properties. Our approach has the advantage of being easier to understand.

An analysis of the structure and complexity of nonlinear binary sequence generators

A method of analysis is presented for the class of binary sequence generators employing linear feedback shift registers with nonlinear feed-forward operations. This class is of special interest because the generators are capable of producing very long "unpredictable" sequences. The period of the sequence is determined by the linear feedback connections, and the portion of the total period needed to predict the remainder is determined by the nonlinear feed-forward operations. The linear feedback shift registers are represented in terms of the roots of their characteristic equations in a finite field, and it is shown that nonlinear operations inject additional roots into the representation. The number of roots required to represent a generator is a measure of its complexity, and is equal to the length (number of stages) of the shortest linear feedback shift register that produces the same sequence. The analysis procedure can be applied to any arbitrary combination of binary shift register generators, and is also applicable to the synthesis of complex generators having desired properties. Although the discussion in this paper is limited to binary sequences, the analysis is easily extended to similar devices that generate sequences with members in any finite field.

Shift-register synthesis and BCH decoding

It is shown in this paper that the iterative algorithm introduced by Berlekamp for decoding BCH codes actually provides a general solution to the problem of synthesizing the shortest linear feedback shift register capable of generating a prescribed finite sequence of digits. The shift-register approach leads to a simple proof of the validity of the algorithm as well as providing additional insight into its properties. The equivalence of the decoding problem for BCH codes to a shift-register synthesis problem is demonstrated, and other applications for the algorithm are suggested.