Short Circuit Safe Operating Area Research Articles

Performance Improvement of Trench-Gate SiC MOSFETs by Localized High-Concentration N-Type Ion Implantation

Gate oxide reliability of a trench-gate SiC MOSFET can be improved by incorporating a gate protection structure, but the resulting parasitic JFET resistance is one major drawback. For reduction of on-resistance, a new method of localized high-concentration n-type doping in JFET regions (JD) is developed. Utilizing process and device simulation by TCAD, the optimal condition of JD that enables maximum device performance is derived. By fabricating a device with the optimal JD structure, the on-resistance is successfully reduced by 25% compared to a conventional device without JD, while maintaining the withstand voltage and the gate oxide electric field at the same level. As a result, a device exhibiting a specific on-resistance of 1.84 mΩcm2 and a breakdown voltage of 1560 V is obtained. The optimal JD structure maintains the short-circuit safe operation area comparable to that for the structure without JD. Thus, by reducing the JFET resistance while minimizing effects on other characteristics, localized JD is shown to be an effective means of realizing a reliable, low-resistance SiC power device.

Simulation Study of a Novel Snapback Free Reverse-Conducting SOI-LIGBT With Embedded P-Type Schottky Barrier Diode

In this article, a novel reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with embedded diode and p-type Schottky Barrier Diode (p-SBD) is proposed. The two diodes are connected in series through a floating electrode, which provides a current path for carriers in reverse-conducting mode. Compared with the Separated Shorted-Anode RCLIGBT (SSA-RC-LIGBT), the proposed structure not only eliminates the snapback voltage ( $\Delta {V}_{\text {SB}}$ ) but also avoids the waste of device area. Therefore, the superior reverse recovery characteristics and excellent tradeoff relationship between ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ) are obtained. The reverse recovery charge of the proposed RC-LIGBT shows 43.9% and 63.2% reduction compared with those of the SSA-RC-LIGBT with ${L}_{\text {B}}$ (distance between the p+ collector and the shorted n+ collector) being 34 and $64~\mu \text{m}$ , respectively. The turn-off loss of the proposed RC-LIGBT at ${V}_{ \mathrm{\scriptscriptstyle ON}} = {2.6}$ V is reduced by 68.2% and 87.1% compared with those of the SSA-RC-LIGBT with $\sf \Delta {V}_{\text {SB}} = {0.48}$ V and $\sf \Delta {V}_{\text {SB}} = {0.17}$ V, respectively. Moreover, the proposed RC-LIGBT has a self-adjusted collector injection efficiency under different temperatures to dramatically improve the Short Circuit Safe Operation Area (SCSOA).

Investigation of repetitive short-circuit operation of 1200 V IGBTs in the IC-VCE phase space

This work shows an investigation of repetitive Short-Circuit (SC) operation of 1200 V–15 A IGBT far above the Short-Circuit Safe Operating Area (SC-SOA). The goal behind this work was to perform repetitive SC tests with test conditions provoking the formation of current filaments in the short-circuit pulse, which leads to a non-homogeneous heating but not to a destruction. The target was to investigate unknown physical effects that lead to device degradation during the repetitive SC test. The IGBT device shows strong deterioration in its blocking characteristic after it was subjected to several 1000 SC pulses at extremely high SC levels.

Effect of short circuit aging on safe operating area of SiC MOSFET

In this paper, we study the effect of aging of SIC MOSFETs on Short Circuit Safe Operating Area and Reverse Bias Safe Operating Area of SiC MOSFETs. SCSOA and RBSOA are determined using short circuit and unclamped inductive switching tests, respectively. Aging of SiC MOSFETs are performed with repetitive short circuit tests at low dissipated energies, which allows to validate the relevance of evolution of different aging indicators measured during the aging process. The decrease in the dissipated energy leading to failure in short circuit and unclamped inductive switching tests allows to clearly link the evolution of these Safe Operating Areas to the degradation of electrical performances (drain and gate leakage currents and on-state resistance). Obtained results show that a strong increase in the drain and/or gate leakage currents after aging has a great effect on the decrease of Safe Operating Area especially on RBSOA and that on-state resistance increase due to aging process represents less impacts in the evolution of RBSOA than in the case of SCSOA. It is also clear from the obtained results that without any apparent evolution of these leakage currents, the decrease of SCSOA after aging is related to the increase in the on-state resistance.

Investigation and Classification of Short-Circuit Failure Modes Based on Three-Dimensional Safe Operating Area for High-Power IGBT Modules

Insulated-gate bipolar transistor (IGBT) short-circuit failure modes have been under research for many years, successfully paving the way for device short-circuit ruggedness improvement. The aim of this paper is to classify and discuss recent contributions about IGBT short-circuit failure modes, in order to establish the current state of the art and trends in this area. First, the concept of 3-D safe operating area is proposed as the IGBT's operational boundary to divide the device short-circuit failure modes into short-circuit VDC/Vrated-ISC SOA limiting and short-circuit endurance time limiting groups. Then, the discussion is centered on currently reported IGBT short-circuit failure modes in terms of their relationships with the device 3-D short-circuit safe operating area (3D-SCSOA) characteristics. In addition, further investigation on the interaction of 3D-SCSOA characteristics is implemented to motivate advanced contributions in future dependence research of device short-circuit failure modes on temperature. Consequently, a comprehensive and thoughtful review of where the development of short-circuit failure mode research works of IGBT stands and is heading is provided.

Electrical and thermal failure modes of 600 V p-gate GaN HEMTs

A study of electrical and thermal failure modes of 600V p-doped GaN HEMTs is presented, which focuses on the investigation of short-circuit limitations. The electrical failure mode seems to be an electrical field breakdown in the structure which is caused by excessive carrier concentration, rather than primary thermal generated. Accordingly, a thermal failure mode is observed, which features a distinctive behaviour and seems to be similar to schottky-gate HEMTs. Concerning the electrical failure mode, a specific p-gate HEMT short-circuit safe operating area (SCSOA) is presented as a novelty. However, a short-circuit capability of up to 520V can be achieved, regarding the design of the gate-drive circuit.

A Short-Circuit Safe Operation Area Identification Criterion for SiC MOSFET Power Modules

This paper proposes a new method for the investigation of the short-circuit safe operation area (SCSOA) of state-of-the-art SiC MOSFET power modules rated at 1.2 kV based on the variations in SiC MOSFET electrical parameters (e.g., short-circuit current and gate-source voltage). According to the experimental results, two different failure mechanisms have been identified, both reducing the short-circuit capability of SiC power modules with respect to discrete SiC devices. Based on such failure mechanisms, two short-circuit safety criteria have been formulated: 1) the short-circuit-current-based criterion; and 2) the gate-voltage-based criterion. The applicability of these two criteria makes possible the SCSOA evaluation of SiC MOSFETs with some safety margins in order to avoid unnecessary failures during their SCSOA characterization. SiC MOSFET power modules from two different manufacturers are experimentally tested in order to demonstrate the procedure of the method. The obtained results can be used to have a better insight of the SCSOA of SiC MOSFETs and their physical limits.

Comparison of thermal runaway limits under different test conditions based on a 4.5 kV IGBT

This investigation focuses on determining the temperature-dependent leakage current limits which compromise the blocking safe operating area for silicon IGBT technologies. A discussion of a proper characterization method for selecting the maximum rated junction temperature for devices operating at high temperatures is given by comparing the different testing methods: Static performance (including and excluding self-heating effects), Short Circuit Safe Operating area and High-Temperature Reverse Bias. Additionally, a thermal model is used to predict the junction temperature at which thermal runaway takes place. In this paper guidelines are proposed based on the correlation among short circuit withstand capability and off-state leakage current for guarantying reliable operation and ensuring that they are thermally stable under parameter variations. This study is helpful to facilitate application engineers for defining the correct stability criteria and/or margins in respect of thermal runaway.

ワイドバンドギャップ半導体によるパワーデバイスの性能改善と課題

Wide-bandgap semiconductors such as SiC have been studied eagerly as a next generation power devices because of its superior physical property. Though very high carrier density is main reason for superior characteristics of that, there are some problems to realize the predicted performance. One is heat radiation limited by package performance. The other is SCSOA (Short Circuit Safe Operating Area) limited by heat capacity of power device itself. Besides, parasitic inductance of power circuitry affects switching losses and switching speed. High current density operation is the key role to realize the predicted performance, and with that purpose, semiconductor device technology, package technology, and circuit technology must be optimized as the total engineering.

A trench accumulation layer controlled insulated gate bipolar transistor with a semi-SJ structure

A high performance trench insulated gate bipolar transistor which combines a semi-superjunction structure and an accumulation channel (sSJTAC-IGBT) is proposed for the first time. Compared with the TAC-IGBT, the new device not only retains the advantages of the accumulation channel, but also obtains a larger breakdown voltage (BV), a faster turn-off speed and a smaller saturation current level while keeping the on-state voltage drop lower as the TAC-IGBT does as well. Therefore, the new structure enlarges the short circuit safe operating area (SCSOA) and reduces the energy loss during the turn-off process.

A Novel 4H-SiC Fault Isolation Device with Improved Trade-Off between On-State Voltage Drop and Short Circuit SOA

This paper aims to introduce a solid-state fault isolation device (FID) for the short circuit protection application in the power distribution systems. The key performance of a FID is to have a low on-state loss and a strong short circuit safe operating area (SCSOA). As a FID, a novel 15kV 4H-SiC field controlled diode (FCD) with a p+buried layer is proposed to provide an improved trade-off between the on-state forward voltage drop and the saturation current. Dynamic response to the fault and the application example of the proposed FCD are described in this paper.

Trench gate IGBT structure with floating P region

A new trench gate IGBT structure with a floating P region is proposed, which introduces a floating P region into the trench accumulation layer controlled IGBT (TAC-IGBT). The new structure maintains a low on-state voltage drop and large forward biased safe operating area (FBSOA) of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage. In addition, it enlarges the short circuit safe operating area (SCSOA) of the TAC-IGBT, and is simple in fabrication and design. Simulation results indicate that, for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.

Method of Strengthening Safe Operating Area for SOI Lateral Insulated Gate Bipolar Transistor

A new SOI-LIGBT structure with multiple base depths is proposed and experimentally verified to address the imbalanced influence of the depleted-layer to the perimeter and the inner cells in device layout. The new devices are implemented by re-integrating the existing process steps. Compared with conventional structure with only single base depth, the new devices experimentally posses a 1.3 times stronger short-circuit safe operating area (SCSOA), an 18V higher forward-biased SOA, and a 15V higher off-state breakdown voltage. Adverse impact on current capability is barely observed.

Current saturation control in silicon emitter switched thyristors

In this paper a novel Dual Channel Emitter Switched Thyristor (DC-EST) structure with diode diverter connected to the P-base region is shown to provide reduced saturation current density without compromising the on-state voltage drop. During the on-state, the diode diverter does not carry any current and the P-base region is effectively floating in potential, which results in a low on-state voltage drop. During current saturation, as the P-base potential rises, the diode diverter diverts the holes collected in the P-base, thus leading to an improved forward biased safe operating area (FBSOA). The saturation current density is lowered significantly which is desirable to achieve a good short circuit safe operating area (SCSOA). The dynamic clamping behavior of the diode diverter allows for independent optimization of the forward drop and saturation current density. Experimental results are reported to confirm the superior characteristics observed through simulations. The novel diode diverter DC-EST structure is found to be particularly suitable for high voltage (4 kV) applications.

Numerical analysis of short-circuit safe operating area for p-channel and n-channel IGBTs

The mechanisms of destructive failure of an insulated gate bipolar transistor (IGBT) at short-circuit state are discussed. Results from two-dimensional numerical simulation of p-channel and n-channel IGBTs are presented. It is found that there are two types of destructive failure mechanisms: a secondary breakdown and a latchup. Which type is dominant in p-channel and n-channel IGBTs depends on an absolute value of forward voltage mod V/sub CE/ mod . At moderately low mod V/sub CE/ mod , the p-channel IGBT is destroyed by secondary breakdown, and the n-channel IGBT, by latchup. This is due to the difference of a type of flowing carrier crossing a base-collector junction of wide base transistor and ionization rates of electrons and holes. >