Short Channel Research Articles

Steep Slope Field Effect Transistors Based on 2D Materials

AbstractWith field effect transistor (FET) sustained to downscale to sub‐10 nm nodes, performance degradation originates from short channel effects (SCEs) degradation and power consumption increment attributed to inhibition of supply voltage (VDD) scaling down proportionally caused by thermionic limit subthreshold swing (SS) (60 mV dec−1) pose substantial challenges for today's semiconductor industry. To further sustain the Moore's law life, incorporation of new device concepts or new materials are imperative. 2D materials are predicted to be able to combat SCEs by virtue of high carrier mobility maintainability regardless of thickness thinning down, dangling bonds free surface and atomic thickness, which contributes to super gate electrostatic controllability. To overcome increasing power dissipation problem, new device structures including negative capacitance FET (NCFET), tunnel FET (TFET), dirac source FET (DSFET) and the like, which show superiority in decreasing VDD by lowering SS below thermionic limit of 60 mV dec−1 have been brought out. The combination of 2D materials and ultralow steep slope device structures holds great promise for low power‐dissipation electronics, which encompass both suppressed SCEs and reduced VDD simultaneously, leading to improved device performance and lowered power dissipation.

A Quasi-Ballistic Model for Short Channel Monolayer Graphene Field Effect Transistor Including Scattering Effects

In this work, the Landauer approach-based short channel model of a graphene field effect transistor has been presented. The quasi-ballistic and ballistic transport mechanism is explained by this approach for nanoscale transistors. The concept of the virtual source is considered to obtain the carrier density in active regions. Here, we apply the Landauer approach for short-channel graphene field effect transistors relating to the parameter in the virtual source model. The mobility of the model has been improved including various scattering effects like impurity scattering, acoustic phonon scattering, and optical phonon scattering. The dynamic resistance model is considered due to asymmetry transport in the electron branch and hole branch. The proposed model has been verified with several experimental works for model validation. The comparisons of the model simulation with several experimental results that have been reported in the literature match well for different short channel lengths of graphene.

Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs

Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs

Long-term weight loss of distal gastric bypass is moderately superior compared to proximal gastric bypass in patients with a BMI of 37-44 Kg/m2.

The laparoscopic Roux-en-Y gastric bypass (LRYGB) is one of the standard procedures in metabolic surgery. Different limb lengths have been proposed in the past to maximize weight loss (WL) and reduce metabolic complications. Distal gastric bypass surgery with a very short common channel (CC) (up to 100cm) has been often criticized due to frequent side effects such as malnutrition, bone weakening and short-bowel syndrome. We introduced a modified version of a distal LRYGB with a 50-70cm long biliopancreatic limb (BPL) and an intermediate short CC (120-150cm). Our primary goal was to compare the long-term WL between distal and proximal LRYGB in two cohorts of patients. Secondary outcomes were weight regain (WR), insufficient weight loss (IWL), postoperative complications and metabolic changes 5 years after surgery. In this retrospective study we collected data from 160 patients operated between 2014 and 2015, with a BMI of 37-44 Kg/m2. 101 patients underwent a distal and 59 patients a proximal LRYGB in two bariatric centers. WL was calculated as percent of excess of BMI loss (%EBMIL), loss of body mass index (Delta-BMI), percent of excess weight loss (%EWL) and percent of total weight loss (%TWL). Data were collected 3, 6, 9, 12, 24, 48 and 60 months after surgery. The distal LRYGB resulted in significantly better 5-year-WL compared to the proximal bypass in terms of %EBMIL (median at 5 years: 83% vs. 65%, p = 0.001), %TWL (median at 5 years: 32% vs. 26%, p = 0.017) and %EWL (median at 5 years: 65% vs. 51%, p = 0.029), with equal major complications and metabolic alterations. In addition, WR was significantly lower in patients with distal bypass (18% vs. 35%, p = 0.032). Distal LYRGB with a 120-150 long CC results in better WL and WL-maintenance compared to proximal LRYGB without major side effects after five years.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

An analytical model of P+ SiC core-shell JLFETs to analyze the performance for higher breakdown voltages applications

In this article, we proposed a core-shell (CS) architecture that uses the silicon carbide (SiC) as a nanowire for higher breakdown voltages in a Junctionless field effect transistor (JLFET). The P+ core-shell improves the electrostatic integrity and reduces lateral band-to-band tunneling in SiC JLFET. Furthermore, the SiC is wide band gap material which helps to achieve the full volume depletion in JLFET at such short channel lengths. Thus, the OFF-state current in P+ SiC CS JLFET has reduced to 10−16 μA even at temperature 600 K and VDS = 2.0 V. The P+ SiC CS JLFET shows significant performance even at higher drain voltages. Hence, we investigate the P+ SiC CS JLFET for higher breakdown voltages with the impact of higher temperatures. In addition, the impact of higher drain voltages with higher temperatures is also examined. This paper presents an analytical model for P+ SiC CS JLFETs which considers Poisson's equation for nanowires as well as the surface potential at the threshold voltage (Vth) and electric field at the zero point (Ez). The model shows that the surface potential and the electric fields in nanowires are essential for an accurate estimation of the drain current. In addition to the numerical modeling results provided by SILVACO TCAD, the performance of the proposed analytical model was compared with simulation results. The results showed good agreement between the simulations and the proposed compact model. This indicates that the proposed model can be used to provide accurate drain current predictions in nanoscale transistors.

Investigating the inhibition of short channel effects using different materials of gate insulator layers in FinFET

As the evolution of FinFET technology continues, traditional gate insulator materials, such as SiO2, face challenges in meeting the demands of modern applications, especially when it comes to gate leakage current control. Emerging as promising contenders to replace SiO2, materials with higher dielectric constants, notably HfO2 and Si3N4, are drawing significant attention in the semiconductor community. Leveraging the advanced capabilities of tools like Silvaco TCAD, an in-depth analysis was conducted to compare the performance and gate leakage current control abilities of SiO2, HfO2, and Si3N4, utilizing the Quantum examples 3D FinFET model. The findings not only highlight the potential of HfO2 and Si3N4 as worthy replacements for SiO2 but also accentuate the distinct advantages of SiO2, making it particularly well-suited as a substitute. This exploration goes beyond a mere comparison of materials. It dives deep into understanding their behaviors under various operational conditions, laying a foundation for potential breakthroughs and fostering the next wave of innovations in semiconductor technology.

Advancements And Applications of Finfet Technology in Modern Semiconductor Engineering

This comprehensive study presents an in-depth analysis of Fin Field-Effect Transistor (FinFET) technology, a significant innovation in semiconductor technology, focusing on its structural attributes, applications, and future prospects. FinFETs, characterized by their distinctive fin-like channels, are pivotal in overcoming the limitations of traditional MOSFETs, particularly in the context of device miniaturization. The paper begins by exploring the basic theory and structural characteristics of FinFETs, emphasizing their enhanced control over short channel effects and reduced leakage currents in scaled-down devices. Attention is then directed towards the integration of FinFET technology in Static Random-Access Memory (SRAM), detailing how FinFETs contribute to improved stability and efficiency in memory storage. Another crucial application discussed is in the biomedical field, where FinFETs have facilitated the development of advanced instrumentation amplifiers and sensitive sensors, marking a leap in medical electronics. The paper concludes by addressing the challenges encountered by FinFETs as fabrication approaches the 5-7nm scale, including their physical and structural limitations. It also highlights ongoing research in structural modifications and material innovations like Gate-All-Around FETs and alternative materials, underscoring the continued evolution and relevance of FinFET technology in the ever-advancing semiconductor industry.

Design insights into a junctionless nanosheet FET (JL-NSFET) for switching and Analog/RF applications: Device to circuit level assessment

- The advent in semiconductor technology paved the way for electronic industry to place in front row. The nanosheet (NS) device is a type gate all around (GAA) architecture provides an excellent gate electrostatic to suppress the short channel effects (SCEs) and scale it further below sub-7nm technology node. This paper provides a complete design insight from device to circuit of a two sheet NSFET with geometrical variations. All digital and analog/RF parameters are extracted and analyzed based on gate length (LG), sheet thickness (TNS), sheet width (WNS), and spacer material variations. As LG is varied from 8 nm to 12 nm, ION/IOFF is enhanced from 0.249 × 108 to 2.86 × 108 due to improved gate control over the channel region which is also reflected in DIBL to 40.82 % whereas, at lower LG analog/RF metrics are better. The TNS play a vital role in device characteristics, as TNS decreases the chance of interaction of electric field from source to drain decreases owing to full volume conduction and thereby ameliorated performance of JL NSFET. As TNS is varied from 7 nm to 5 nm, all electrical characteristics are improved and analog/RF parameters gm, Av, fT, TFP and GTFP are improved to 10.3 %, 18.4 %, 12.1 % 18.5 % and 54.04 %, respectively. Increase in WNS from 10 nm to 20 nm results into increased effective width of a device, it leads to higher ION current which further impacts on electrical and analog/RF parameters. The DIBL, gm, fT, GFP, TFP and GTFP are enhanced to 63.7 %, 37.9 %, 34.9 %, 9.7 %, 33.5 %, 9.1 %, respectively. The spacer materials are varying from Al2O3 (k = 18), HfO2 (k = 22), ZrO2 (k = 25) to TiO2 (k = 44), the electrical characteristics are better at higher-k whereas analog/RF performances are superior at lower-k. Further, digital circuit elements NOT, NAND and NOR gates are designed, simulated and the delays are examined as 4.25ps, 6.45ps and 5.12ps, respectively. The NML and NMH of NOT gate are noticed as 295 mV and 280 mV at 0.7 V of supply voltage. Furthermore, a common source (CS) amplifier is also simulated and gain of 3.3 is noticed. The aforementioned analysis revels the JL NSFET is best suitable candidate for future nanoscale applications.

Simulation of Voltage Applied Effect on Carbon-Doped Boron Nitride Nanoribbon Hydrogen Gas Sensing Performance

Advanced materials have been widely investigated for numbers of electronics application. The aim is to provide higher device performance and mitigating the short channel effect. In this work, the performance of hydrogen sensing on carbon-doped boron nitride nanoribbon (BC2NNR) is investigated in response to different gate voltage applied, Vgs. The simulation is done to see the variation in the density of state (DOS) and the variation in the I – V characteristic. From the simulation, a significant effect is found when the Hydrogen gas was attached to different atom positions within the BC2NNR surface. A notable difference in sensitivity was achieved when Vgs is varied from 0 V to 2 V. In fact, a sensitivity of 85.07 % was achieved when the hydrogen molecule was attached to carbon atom. The result presented here may become guideline for experimentalists fabricating BC2NNR for gas sensing application.

Sensitivity improvement in gate engineered technique dielectric modulated GaN MOSHEMT with InGaN notch for label-free biosensing

This paper focuses on the impact of gate-engineered dielectric-modulated GaN MOSHEMT with InGaN notch on sensitivity enhancement for label-free biosensing. The novelty of this study utilizes the charge-plasma effect induced by the dual metal gate (DMG) technology adopted to realize the effect of sensitivity on different biomolecules. Moreover, the presence of an InGaN notch enhances carrier confinement in the 2DEG, subsequently improving the threshold voltage and device sensitivity at the AlGaN/GaN interface. The maximum drain current, IDS of 4.602 A mm−1, transconductance, gm of 18 mS/mm, and sensitivity has been improved by around 61% for the Uricase biomolecule by introducing the dual metal gate technology. The work function difference of the two metal gates suppresses the Short Channel Effects (SCEs) and hot carrier effects in DMG MOSHEMT, thereby screening the drain potential variations by the gate near the drain. In addition, increased carrier transport efficiency results from a more consistent electric field along the channel. All the simulations are carried out using the Sentaurus TCAD simulator, and the results imply the feasibility of gate-engineered GaN MOSHEMT for label-free biosensing.

Bias-dependent electron velocity and short-channel effect in scaling sub-100 nm InAlN/GaN HFETs

This work reports on the extraction and simulation of the electron velocity–gate voltages relationship for sub-100 nm InAlN/GaN heterojunction field-effect transistors (HFETs). A peak electron velocity (ve) at an electron density (ns) of 0.41 × 1013 cm−2 was observed at 1.06 × 107 cm/s in an InAlN/GaN HFET with 60 nm gate length (Lg) by delay time analysis. The ve at a high ns of 1.5 × 1013 cm−2 was observed at 0.6 × 107 cm/s. This peak ve behavior is explained by polarization Coulomb field (PCF) scattering and optical phonon scattering based on a Monte Carlo method. As Lg scaled from 350 to 60 nm, the current gain cutoff frequency (fT) and transconductance (gm) were improved. However, the thermal performance was degraded with a bad figure of merit P150 °C. Although a weakening of the control capability of Vgs on ns (Δns/ΔVgs) was observed in the shorter Lg device, which leads to a decrease in device gm, the larger electron velocity by the increased lateral electric field (E) and the larger Δve/ΔVgs by the increased PCF scattering still enhance the peak gm. Results indicate that the enhancement of Δve/ΔVgs is a vital method to strengthen the modulation of the gate on current and to suppress the short channel effect in GaN HFET. Our work supports a deeper understanding and analysis of sub-100 nm InAlN/GaN HFET device performance and physical mechanisms.

Optimizing dielectric constants for enhanced performance in nanoscale DG-FinFETs: A comprehensive study on short channel effects

This study explores how variations in fin and gate dielectric constants impact nanoscale, DG-FinFETs’ sensitivity to Short Channel Effects (SCEs). Various fin (channel) materials; Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si), are considered. PADRE simulation environment is used to investigate the threshold Voltage (Vth) Roll-off, a crucial performance parameter. GaAs-FinFET, with a gate dielectric and fin dielectric constant values of 15 and 45 shows the lowest threshold voltage of 0.412 V. The study concludes that FinFETs with a higher fin dielectric constant than gate dielectric constant exhibit reduced SCEs, leading to lower power consumption, faster switching, and improved efficiency. This underscores the importance of optimizing dielectric constants, especially the fin dielectric constant, for enhanced DG-FinFET performance.

Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications

Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Semiconductor devices used in radiation environment are more prone to degradation in device performance. Junctionless Tunnel Field Effect Transistor (JLTFET) is one of the most potential candidates which overcomes the short channel effects and fabrication difficulties. In this work, 20 nm JLTFET is proposed with Silicon in the drain/channel region whereas source uses different materials, Silicon Germanium (SiGe), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Arsenide (InAs). The device performance is examined by subjecting it to heavy ion radiation at a lower and higher dose of linear energy transfer (LET) values. It can be seen that the most sensitive location is the source/channel (S/C) interface for SiGe, GaN and GaAs whereas the drain/channel (D/C) interface for InAs. Further analysis is carried out at these vulnerable regions by matching ION of all materials. The parameters, transient peak current (Ipeak), collected charge (QC), threshold voltage shift (ΔVth) and bipolar gain (β) are extracted using transient simulations. It is observed that for a lower dose of LET, Ipeak of SiGe is 27% lesser than InAs and for higher dose of LET, SiGe shows 56% lesser Ipeak than InAs. SiGe is less sensitive at lower and higher dose of LET due to reduced ΔVth, tunneling and electron density.

Impact of work function metal stacks on the performance and reliability of multi-Vth RMG CMOS technology

Multi-Vth CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device Vth’s are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-Vth and ultra-high Vth pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.

Agricultural distribution channels under pressure and stress for farmers to access markets

ABSTRACT While long supply chains remain the dominant model, other forms of distribution are being (re)constructed or reaffirmed, namely short channels and hybrid channels. The aim of this article is to understand whether a farmer’s choice of distribution channel has an impact on tensions at work. More specifically, the aim is to analyse whether various stresses differ according to the type of distribution, whether one distribution channel seems preferable to another in terms of limiting the stresses experienced and/or perceived by farmers, and whether it is possible to limit work-related stresses a priori, when constructing the channel. This analysis was carried out on an exploratory and qualitative basis, using individual and group interviews with a sample of farmers in a mountainous area. Our results identify sources of work-related tension for each type of distribution. This original work focuses on the upstream side of the channel. It explains the various tensions at work and identifies ways of managing them during the construction of a channel.

Investigation of RF performance of Ku-band GaN HEMT device and an in-depth analysis of short channel effects

In this paper, we have characterized an AlGaN/GaN High Electron Mobility Transistor (HEMT) with a short gate length (Lg ≈ 0.15 μm). We have studied the effect of short gate length on the small signal parameters, linearity parameters and gm-gd ratio in GaN HEMT devices. To understand how scaling results in the variation of the above-mentioned parameters a comparative study with higher gate length devices on similar heterostructure is also presented here. We have scaled down the gate length but the barrier thickness(tbar) remained same which affects the aspect ratio (Lg/tbar) of the device and its inseparable consequences are the prominent short channel effects (SCEs) barring the optimum output performance of the device. These interesting phenomena were studied in detail and explored over a temperature range of −40 °C to 80 °C. To the best of our knowledge this paper explores temperature dependence of SCEs of GaN HEMT for the first time. With an approach to reduce the impact of SCEs a simulation study in Silvaco TCAD was carried out and it is observed that a recessed gate structure on conventional heterostructure successfully reduces SCEs and improves RF performance of the device. This work gives an overall view of gate length scaling on conventional AlGaN/GaN HEMTs.

Threshold voltage modeling based comparative performance exploration of Junctionless and Junction-Based High-K gate stack Dual-Material Cylindrical Gate-All-Around Macaroni MOSFET

This paper presents explicit threshold voltage modeling based comparative threshold voltage exploration of Junctionless (JL) and Junction-based (JB) High-K gate stack (HKGS) Dual-Material (DM) Cylindrical Gate-all-around (CGAA) Macaroni (Mac.) MOSFET. Based on Young’s popular Parabolic Potential Approximation (PPA), device features like inner potential has been formulated. Based on the expression of inner potential, threshold voltage has been extracted. Other major short channel effects like Drain-induced barrier lowering (DIBL) and subthreshold swing (SS) have also been analyzed. Device parameters such as inner, outer radii, channel lengths, type of high-k gate oxide, source/drain doping for JB device, etc. have also been varied to examine their effects on device parameters. Finally mathematical outputs have been corroborated with simulation outputs from Atlas.

A detachable interface for stable low-voltage stretchable transistor arrays and high-resolution X-ray imaging

Challenges associated with stretchable optoelectronic devices, such as pixel size, power consumption and stability, severely brock their realization in high-resolution digital imaging. Herein, we develop a universal detachable interface technique that allows uniform, damage-free and reproducible integration of micropatterned stretchable electrodes for pixel-dense intrinsically stretchable organic transistor arrays. Benefiting from the ideal heterocontact and short channel length (2 μm) in our transistors, switching current ratio exceeding 106, device density of 41,000 transistors/cm2, operational voltage down to 5 V and excellent stability are simultaneously achieved. The resultant stretchable transistor-based image sensors exhibit ultrasensitive X-ray detection and high-resolution imaging capability. A megapixel image is demonstrated, which is unprecedented for stretchable direct-conversion X-ray detectors. These results forge a bright future for the stretchable photonic integration toward next-generation visualization equipment.