Short-channel PMOS Devices Research Articles

Compressive Uniaxial Stress Bandstructure Engineering for Transferred-Hole Devices

The transport properties of holes in Si, Ge, and Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge under high compressive stresses are studied with a Monte Carlo simulation method. Stress significantly improves the low-energy mass and mobility, while its effect is diminished in the high-energy bandstructure. The transient behavior of the carrier velocity exhibits a double-overshoot peak at high driving field. This double-overshoot behavior is manifested in carrier-velocity profiles in simulated short-channel PMOS devices. In steady state at lower field, the hole velocity exceeds the saturation velocity at high field. This leads to a negative differential resistance effect in simulated resistors. We propose to use this effect, generic to cubic semiconductors, for transferred-hole devices. An advantage of this approach is that it can be integrated into the conventional stress-engineered Si or Ge logic process.

Substrate bias effects on drain-induced barrier lowering in short channel PMOS devices at 77 K

Experimental results on the substrate biasing characteristics of drain-induced barrier lowering (DIBL) in short channel PMOS devices with boron ion channel doping at 77 K are presented in detail. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and thereafter began decreasing. The new version of the two-dimensional device simulation program, MINIMOS 4.0, suitable for MOS simulation at cryogenic temperatures, was used to investigate this unique feature, which could be explained as the transition of surface DIBL to subsurface DIBL and the onset of punch-through. A new empirical model for describing the substrate characteristics of DIBL was developed: R = δV TH(DIBL)/ δV DS = αL − β , α = α o + α 1 V BS, β = β O + β 1 V BS. It is used for quantitative comparisons between 300 and 77 K based on the test PMOS device measurements. The extracted values of α O and α 1 (representing δV DIBL at V BS = OV and the slope of R versus V BS for the L = 1 μm device) were decreased by 27.5% and increased by 42%, respectively, from 300 to 77 K. The corresponding values of β 0 and β 1 (representing the curvature of δV DIBL versus L at V BS = OV and the slope of this curvature versus V BS) were decreased by 9 and 4%, respectively, for the same temperature reduction. These results clearly show the improvement of DIBL at 77 K, especially for smaller V BS, and could be explained physically by the decrease of the source (drain)-to-channel depletion width and partial carrier freeze-out effect in the substrate. Further simulations were carried out by MINIMOS 4.0 with the emphasis on the boron ion channel doping profile. By changing the channel implantation dose from 4.3 × 10 11 to 8.7 × 10 11 cm −2 and energy from 25 to 35 keV, the extracted parameters of α and β were found to be very sensitive to both implantation dose and energy.

The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K

This paper presents detailed experimental results on the substrate biasing characteristics of drain-induced barrier lowering DIBL at 77 K in short channel PMOS devices with boron ion channel doping. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias, and thereafter began decreasing. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique feature of DIBL vs substrate biasing. From the simulation results, the dependence of DIBL on substrate biasing could be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias-dependent characteristics of DIBL: (R) = δV TH (DIBL) δV DS = αL −β , α = α 0 + α 1 V BS, β = β 0 + β 1 V BS has been developed, and using this model, quantitative comparisons between 77 and 300 K results were made. These comparisons clearly show the improvement of DIBL at 77 K, especially for shorter channel devices. The experimental results could be explained physically by the transition of the subsurface current flow towards the surface current flow due to higher surface potential bending at 77 K. Further analysis were carried out with the emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile. It was found that the extracted parameters α and β were very sensitive to the channel implant dose and energy, but were only slightly related to the threshold voltage definition.

Substrate bias effects on drain-induced barrier lowering in short-channel PMOS devices

It was found that, as the channel length decreased, the threshold voltage shift caused by drain-induced barrier lowering (DIBL) first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (L/sub INT/) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 and 0.90 mu m for the PMOS devices. This change in DIBL with substrate bias for devices with varying L can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, an empirical model for describing this substrate bias characteristic of the DIBL effect is developed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>