Short-channel Nanowire Research Articles

Suppressing the excess OFF-state current of short-channel InAs nanowire field-effect transistors by nanoscale partial-gate

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue particularly in short-channel nanowire (NW) field-effect transistors (FETs), especially for narrow bandgap semiconductors such as InAs. Here, to clarify the components of the OFF-current and suppress the OFF-current, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG). We fabricate a series of PGFETs and a normal full-gate (FG) FET on the same NW. Based on our results, the BTBT current component can reach tens of nanoamps in a typical 250 nm-channel InAs NW FGFET, and dominate the OFF-current. In contrast, there is almost no BTBT component in the PGFET, which provides a reference for other short-channel InAs NW FETs. Furthermore, the physical mechanism of the OFF-state carrier transport is discussed, and both electrons and holes currents are proven to be very important, based on our experimental results. Also, through statistic study, we find the BTBT effect can be more serious in the devices with better gate-control. Therefore, suppressing the BTBT effect is important to the future scaling-down.

(Invited) The Scaling-Down and Performance Optimization of InAs Nanowire Field Effect Transistors

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue for short channel nanowire (NW) field-effect transistors (FETs), especially for semiconductors with narrow bandgap such as InAs. To suppress the OFF-state current and find way to improve the properties of short channel NW FETs based on semiconductors with narrow bandgap, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG). While compared with full-gate (FG) FET fabricated on the same NW, PGFET shows better OFF-state characteristics. Through studying the devices with different length of PG, different measurement conditions and fabrication processes, we find the excess OFF-state leakage current is mainly induced by the BTBT caused by the high-field at the drain-end of the channel, which can be obviously suppressed by the ungated region of PGFET. Through statistic study, we find BTBT effect can be more serious in the devices with better gate-control.

A compact 2D potential model for subthreshold characterization of nanoscale fully depleted short channel nanowire MOSFETs

SummaryIn this work, a compact subthreshold model for fully depleted nanoscale short channel nanowire MOSFETs is proposed. It is based on an approximated solution of two‐dimensional Poisson's Equation in cylindrical coordinate system. It matches well with technology computer‐aided design simulation results in a wide range variation of design parameters without introducing any empirical fitting parameters. Copyright © 2014 John Wiley & Sons, Ltd.

Top-Gated Silicon Nanowire Transistors in a Single Fabrication Step

Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO(2) shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing. This natural oxide shell has negligible leakage over the operating range. Our single-step patterning is a most practical route for realization of short-channel nanowire transistors and can be applied to a number of nanodevice geometries requiring nonequivalent electrodes.

Physics based modelling of short-channel nanowire MOSFET

A modelling framework for short channel nanowire (NW) MOSFETs that covers a wide range of operating conditions is presented. The device electrostatics in the subthreshold regime is dominated by the inter-electrode capacitive coupling, which, in the case of double gate (DG) devices, is analyzed in terms of conformal mapping techniques. Previously, we have shown that these results can also be successfully applied to the NW MOSFET, by performing an appropriate mapping to compensate for the difference in gate control between the two devices. Near and above threshold, the influence of the electronic charge is taken into account in a precise, self-consistent manner by combining suitable model expressions with Poisson's equation. The models are verified by comparison with numerical device simulations.