Shift Register Chain Research Articles

4 Gbps serializer circuits in a 180 nm technology for monolithic pixel sensor prototypes developed for the CEPC vertex detector

Monolithic Active Pixel Sensor is one of the promising candidates for the Circular Electron Positron Collider Vertex detector, due to its good performance and trade-off of granularity, readout speed, material budgets and power consumption. A full-scale TaichuPix chip, including a matrix of 512 × 1024 pixels with a size of 25 × 25 μm2 is developed to provide a spatial resolution better than 5 μm. It requires a raw data rate up to 3.84 Gbps and power consumption less than 100 mA for the serializer circuit. Based on one of the small-scale prototypes, the highest serial data rate is tested to be 3.36 Gbps with a peak-to-peak jitter of about 150 ps and large current consumption. Moreover, the 32-bit parallel data width of the serializer isn't suitable for the 8B10B encoder. Therefore, two 4 Gbps serializers have been designed and optimized to meet these requirements based on the same process node of 180 nm as the TaichuPix, considering the funding and time costs. The serializer consists of a phase locked loop (PLL), several 5:1 sub-multiplexers based on a shift-register chain, a 4:1 or 8:1 sub-multiplexer based on the binary-tree structure, a clock distributor and a high-speed driver. Both ring-oscillating PLL and LC-tank PLL were integrated for performance evaluation. The preliminary tests showed low-jitter characteristics of the two PLLs despite this version's biasing problem, and both serializer circuits functioned correctly. A revision corrected the error and was submitted in October 2023.

Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies

Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.

Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

Single Event Upset Sensitivity of D-Flip Flop: Comparison of PDSOI With Bulk Si at 130 nm Technology Node

Single-event upsets are studied in digital storage cells in 130nm CMOS bulk Si and PDSOI technologies. The sensitivity of SEU to different technologies and hardening approaches is explored by using heavy-ion radiation experiments. Error numbers in D flip-flop chains are used to determine the impact of various cell designs and PDSOI hardening technique on upset sensitivity. Various flip-flops are designed and connected as shift-register chains, and the error numbers induced by irradiation are recorded to examine the effectiveness of the PDSOI technology. It was found that PDSOI technology has better performance in terms of upset robustness versus bulk Si at the 130nm technology node. The same design structure implemented in PDSOI technology has higher SEU threshold LET and much lower saturation cross section due to its full dielectric isolation structure which does not allow the charge generated in the substrate to be collected by the electrically active junctions in the thin top region of the device and reduces the sensitive volume of p-n junctions in the transistor. As shown in the experiment result, NRH_SOI (not radiation hardening SOI) saves about 25% area while having much lower SER versus DICE_Si, which means PDSOI still has obvious advantage at reducing SEU rate, even though its necessary body contact has to consume certain extra area.

Single Event Resilient Dynamic Logic Designs

Dynamic logic families are commonly used in high speed applications, but they are susceptible to single event errors. This paper presents and evaluates three techniques of hardening dynamic logic--layout manipulation using charge sharing, addition of a feedback capacitor across the static inverter, and dual-rail domino logic with differential keepers. The layout-based design has better single event tolerance by sharing charge between NFET devices of the dynamic and static inverters; the design with a feedback capacitor makes the keeper more effective in recovering the hit node because of the increased propagation delay; the differential-keeper structure shows superior SET performance because the hit node could recover through the restoring path in the case of charge loss. These proposed designs along with the reference traditional keeper-based design were fabricated in a 130 nm technology node as shift register chains and then irradiated by heavy ion particles. Experimental results verified the mechanisms and effectiveness of these proposed designs.

A low noise multi-channel readout IC for X-ray cargo inspection

A low noise multi-channel readout integrated circuit (IC) which converts a detector current to analog voltage for X-ray cargo inspection is described. The readout IC provides 32 channels of a circuit having a maximum dynamic range of 15 bit and is comprised of integrator gain selection, timing generator, shift register chain, integrator array, sample/hold (S/H) stage amplifier etc. It was fabricated using 0.6 μm standard CMOS process, and occupies a die area of 2.7 × 13.9 mm2. It operates at 1 MHz, consumes 100 mW from a 5 V supply and 4.096 V as reference, and has a measured output noise of 85 μ Vrms on 63 pF of integrator gain capacitance and 440 pF of photodiode terminal capacitance so that steel plate penetration thickness can reach more than 400 mm.

Design and implementation of a programming circuit in radiation-hardened FPGA

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

IEEE 1149.1의 실시간 신호 시험 구조 설계

보드에 장착된 소자들을 테스트하기위해 제안된 IEEE 1149.1 시험 구조는 입력으로 TDI 핀을 사용하고 출력으로 TDO 핀을 사용하는 커다란 직렬 쉬프트 레지스터이다. IEEE 1149.1은 보드 수준에서의 테스트는 완벽하게 수행하지만 보드가 시스템에 장착되고 난 후의 수행 중인 시스템 수준에서의 실시간 동작클럭 속도로의 테스트에는 문제가 있다. 즉시험대상 핀의 실시간 동작신호를 시험하기 위하여 직렬 시프트 레지스트 체인들의 출력속도를 동작 클럭의 쉬프트레지스터 배수 이상의 속도로 작동 하여야 한다. 본 논문에서는 시스템 클럭과 동일한 속도로 실시간 신호를 캡쳐하기 위한 실시간 신호 시험 구조를 설계하고 시험 절차를 제안하였다. 제안한 실시간 신호 시험 구조를 Altera의 Max+Plus 10.0을 사용하여 제안한 시험 절차에 따라 시뮬레이션을 수행하였으며, 이를 통해 제안한 시험구조가 정확히 동작함을 확인하였다. IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping

Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.

An Area and Power Efficient Radiation Hardened by Design Flip-Flop

A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> /mg) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

Staggered voting for TMR shift register chains in poly‐Si TFT‐LCDs

This paper presents the idea of staggered voting for the efficient TMR implementation of shift register chains for improving the yield of Poly‐Si TFT‐LCD driving circuits. The paper discusses the characteristic features of staggered voting and performs a quantitative evaluation of its effectiveness. Staggered voting allows us to improve the reliability of a single‐voter TMR chain significantly when the probability of a voter failure is not negligible.

Optical programming of floating gate MOS switches for test and reconfiguration

This paper describes a new optical programming method for floating gate MOS devices. They can be used in shadow memories that control interconnection switches for testing and fixing the configuration of monolithically integrated systems, such as Programmable Gate Arrays or systems using redundant modules for yield or reliability enhancement. The feasibility of the optical programming has been shown first on usual stacked-gate devices using a 257 nm UV beam. Their programming behaviour has been theoretically explained and successfully simulated. An even simpler single-poly structure can be used which is yet more suitable for optical programming. Circuits are described for a variety of application modes. They use either an optical data injection by a scanned UV-beam or an electrical data injection by a shift register chain or random access. In the case of electrical data injection, the floating gate device is part of a flip-flop, where the data are later frozen in by an indiscriminate UV-flash.

Electronic organ circuit

An electronic organ circuit includes a multiplicity of keyers receiving control inputs from plural shift and store registers capable of operating any given keyer at different levels. The inputs for a given keyer are applied on a cyclic basis and for differing time periods in such manner that the keyer's output amplitude and waveshape vary in response to the number and duration of inputs. A processor responsive to keyboard key and stop actuation supplies information to shift register chains corresponding bit-wise to the operation of keyboard keys, and corresponding, in respect to bits destined for a given register, to the condition of organ stops. Individual registers are then operated on a duty cycle basis and provide outputs of selected duration for effecting different stop sounds.