4 Gbps serializer circuits in a 180 nm technology for monolithic pixel sensor prototypes developed for the CEPC vertex detector

Abstract

Monolithic Active Pixel Sensor is one of the promising candidates for the Circular Electron Positron Collider Vertex detector, due to its good performance and trade-off of granularity, readout speed, material budgets and power consumption. A full-scale TaichuPix chip, including a matrix of 512 × 1024 pixels with a size of 25 × 25 μm2 is developed to provide a spatial resolution better than 5 μm. It requires a raw data rate up to 3.84 Gbps and power consumption less than 100 mA for the serializer circuit. Based on one of the small-scale prototypes, the highest serial data rate is tested to be 3.36 Gbps with a peak-to-peak jitter of about 150 ps and large current consumption. Moreover, the 32-bit parallel data width of the serializer isn't suitable for the 8B10B encoder. Therefore, two 4 Gbps serializers have been designed and optimized to meet these requirements based on the same process node of 180 nm as the TaichuPix, considering the funding and time costs. The serializer consists of a phase locked loop (PLL), several 5:1 sub-multiplexers based on a shift-register chain, a 4:1 or 8:1 sub-multiplexer based on the binary-tree structure, a clock distributor and a high-speed driver. Both ring-oscillating PLL and LC-tank PLL were integrated for performance evaluation. The preliminary tests showed low-jitter characteristics of the two PLLs despite this version's biasing problem, and both serializer circuits functioned correctly. A revision corrected the error and was submitted in October 2023.