Shared Memory Architecture Research Articles

Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator

<p>This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.</p>

A collaborative CPU–GPU approach for principal component analysis on mobile heterogeneous platforms

The advent of the modern GPU architecture has enabled computers to use General Purpose GPU capabilities (GPGPU) to tackle large scale problem at a low computational cost. This technological innovation is also available on mobile devices, addressing one of the primary problems with recent devices: the power envelope. Unfortunately, recent mobile GPUs suffer from a lack of accuracy that can prevent them from running any large scale data analysis tasks, such as principal component analysis (Shlens, 0000) (PCA). The goal of our work is to address this limitation by combining the high precision available on a CPU with the power efficiency of a mobile GPU. In this paper, we exploit the shared memory architecture of mobile devices in order to enhance the CPU–GPU collaboration and speed up PCA computation without sacrificing precision. Experimental results suggest that such an approach drastically reduces the power consumption of the mobile device while accelerating the overall workload. More generally, we claim that this approach can be extended to accelerate other vectorized computations on mobile devices while still maintaining numerical accuracy.

Symmetric Indefinite Linear Solver Using OpenMP Task on Multicore Architectures

Recently, the Open Multi-Processing (OpenMP) standard has incorporated task-based programming, where a function call with input and output data is treated as a task. At run time, OpenMP’s superscalar scheduler tracks the data dependencies among the tasks and executes the tasks as their dependencies are resolved. On a shared-memory architecture with multiple cores, the independent tasks are executed on different cores in parallel, thereby enabling parallel execution of a seemingly sequential code. With the emergence of many-core architectures, this type of programming paradigm is gaining attention—not only because of its simplicity, but also because it breaks the artificial synchronization points of the program and improves its thread-level parallelization. In this paper, we use these new OpenMP features to develop a portable high-performance implementation of a dense symmetric indefinite linear solver. Obtaining high performance from this kind of solver is a challenge because the symmetric pivoting, which is required to maintain numerical stability, leads to data dependencies that prevent us from using some common performance-improving techniques. To fully utilize a large number of cores through tasking, while conforming to the OpenMP standard, we describe several techniques. Our performance results on current many-core architectures—including Intel’s Broadwell, Intel’s Knights Landing, IBM’s Power8, and Arm’s ARMv8—demonstrate the portable and superior performance of our implementation compared with the Linear Algebra PACKage (LAPACK). The resulting solver is now available as a part of the PLASMA software package.

Searching for common patterns on protein sequences by means of a parallel hybrid honey-bee mating optimization algorithm

Abstract At present, most computing systems have multiple cores accessing to a shared memory space. In the case of computing systems devoted to research, it is common to cluster several shared memory architectures together in order to go beyond the limits of a single shared memory architecture. These clusters can represent a significant resource for those researchers who accomplish to exploit them to the fullest. One of the most applied techniques to achieve this purpose is the mixed mode parallel programming which combines both OpenMP and MPI paradigms. In this paper, we present a parallel implementation of a swarm-based evolutionary algorithm designed for solving a complex biological optimization problem. In order to obtain the maximum possible performance, we have combined MPI and OpenMP. Furthermore, in order to solve the addressed problem in a realistic way, we have applied multiobjective optimization. For assessing the performance achieved by our proposal we have conducted experiments under different systems on six biological instances with different sizes. Results point out the relevance of combining mixed mode parallel programming, a swarm-based evolutionary algorithm, and multiobjective optimization from both parallelism and biology points of view.

Anytime parallel density-based clustering

The density-based clustering algorithm DBSCAN is a state-of-the-art data clustering technique with numerous applications in many fields. However, DBSCAN requires neighborhood queries for all objects and propagation of labels from object to object. This scheme is time consuming and thus limits its applicability for large datasets. In this paper, we propose a novel anytime approach to cope with this problem by reducing both the range query and the label propagation time of DBSCAN. Our algorithm, called AnyDBC, compresses the data into smaller density-connected subsets called primitive clusters and labels objects based on connected components of these primitive clusters to reduce the label propagation time. Moreover, instead of passively performing range queries for all objects as in existing techniques, AnyDBC iteratively and actively learns the current cluster structure of the data and selects a few most promising objects for refining clusters at each iteration. Thus, in the end, it performs substantially fewer range queries compared to DBSCAN while still satisfying the cluster definition of DBSCAN. Moreover, by processing queries in block and merging the results into the current cluster structure, AnyDBC can be efficiently parallelized on shared memory architectures to further accelerate the performance, uniquely making it a parallel and anytime technique at the same time. Experiments show speedup factors of orders of magnitude compared to DBSCAN and its fastest variants as well as a high parallel scalability on multicore processors for very large real and synthetic complex datasets.

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures

High-end embedded systems, like their general-purpose counterparts, are turning to many-core cluster-based shared-memory architectures that provide a shared memory abstraction subject to non-uniform memory access costs. In order to keep the cores and memory hierarchy simple, many-core embedded systems tend to employ simple, scratchpad-like memories, rather than hardware managed caches that require some form of cache coherence management. These “coherence-free” systems still require some means to synchronize memory accesses and guarantee memory consistency. Conventional lock-based approaches may be employed to accomplish the synchronization, but may lead to both usability and performance issues. Instead, speculative synchronization, such as hardware transactional memory, may be a more attractive approach. However, hardware speculative techniques traditionally rely on the underlying cache-coherence protocol to synchronize memory accesses among the cores. The lack of a cache-coherence protocol adds new challenges in the design of hardware speculative support. In this article, we present a new scheme for hardware transactional memory (HTM) support within a cluster-based, many-core embedded system that lacks an underlying cache-coherence protocol. We propose two alternative data versioning implementations for the HTM support, Full-Mirroring and Distributed Logging and we conduct a performance comparison between them. To the best of our knowledge, these are the first designs for speculative synchronization for this type of architecture. Through a set of benchmark experiments using our simulation platform, we show that our designs can achieve significant performance improvements over traditional lock-based schemes.

Parallel synchronous and asynchronous coupled simulated annealing

We propose a parallel synchronous and asynchronous implementation of the coupled simulated annealing (CSA) algorithm in a shared-memory architecture. The original CSA was implemented synchronously in a distributed-memory architecture. It synchronizes at each temperature update, which leads to idling and loss of efficiency when increasing the number of processors. The proposed synchronous CSA (SCSA) is implemented as the original, but in a shared-memory architecture. The proposed asynchronous CSA (ACSA) does not synchronize, allowing a larger parallel efficiency for larger numbers of processors. Results from extensive experiments show that the proposed ACSA presents much better quality of solution when compared to the serial and to the SCSA. The experiments also show that the performance of the proposed ACSA is better than the SCSA for less computationally intensive problems or when a larger number of processing cores are available. Moreover, the parallel efficiency of the ACSA improves by increasing the size of the problem. With the advent of the Multi-core Era, the use of the proposed algorithm becomes more attractive than the original synchronous CSA.

Numerical Solution and Analysis of Three-Dimensional Transient Darcy Flow

This paper presents a detailed analysis of a numerical solution of three-dimensional transient Darcy flow. The numerical solution of the governing parabolic partial differential equations is obtained by using stabilized mixed Galerkin method and backward Euler method for the discretization of space and time, respectively. The resulting well-posed system of algebraic equations is subsequently solved using conjugate gradient method. The proposed model is validated against Mongan’s analytical model for underground water flow using a set of hexahedral and tetrahedral meshes. The model is used to analyze the transient behavior by simulating the Darcy flow through homogeneous and heterogeneous as well as isotropic and anisotropic media. For large meshes, a parallel algorithm of the transient Darcy flow is also developed for shared memory architecture using OpenMP library. For structured meshes, a speedup of over 22 is obtained on dual AMD Opteron processors. The proposed numerical method for transient Darcy flow offers stability, ease of implementation in higher dimensions and parallel solution for large and complex geometry using standard finite element spaces.

Parallelization of elliptic solver for solving 1D Boussinesq model

In this paper, a parallel implementation of an elliptic solver in solving 1D Boussinesq model is presented. Numerical solution of Boussinesq model is obtained by implementing a staggered grid scheme to continuity, momentum, and elliptic equation of Boussinesq model. Tridiagonal system emerging from numerical scheme of elliptic equation is solved by cyclic reduction algorithm. The parallel implementation of cyclic reduction is executed on multicore processors with shared memory architectures using OpenMP. To measure the performance of parallel program, large number of grids is varied from 28 to 214. Two test cases of numerical experiment, i.e. propagation of solitary and standing wave, are proposed to evaluate the parallel program. The numerical results are verified with analytical solution of solitary and standing wave. The best speedup of solitary and standing wave test cases is about 2.07 with 214 of grids and 1.86 with 213 of grids, respectively, which are executed by using 8 threads. Moreover, the best efficiency of parallel program is 76.2% and 73.5% for solitary and standing wave test cases, respectively.

An effective fusion and tile size model for optimizing image processing pipelines

Effective models for fusion of loop nests continue to remain a challenge in both general-purpose and domain-specific language (DSL) compilers. The difficulty often arises from the combinatorial explosion of grouping choices and their interaction with parallelism and locality. This paper presents a new fusion algorithm for high-performance domain-specific compilers for image processing pipelines. The fusion algorithm is driven by dynamic programming and explores spaces of fusion possibilities not covered by previous approaches, and is driven by a cost function more concrete and precise in capturing optimization criteria than prior approaches. The fusion model is particularly tailored to the transformation and optimization sequence applied by PolyMage and Halide, two recent DSLs for image processing pipelines. Our model-driven technique when implemented in PolyMage provides significant improvements (up to 4.32X) over PolyMage's approach (which uses auto-tuning to aid its model), and over Halide's automatic approach (by up to 2.46X) on two state-of-the-art shared-memory multicore architectures.

Thread-parallel mesh improvement using face and edge swapping and vertex insertion

The purpose of this paper is three-fold. First, we devise a memory model for unstructured mesh data for efficient use of memory on parallel shared memory architectures, with the purpose of lowering the synchronization overhead between threads while avoiding race conditions. Second, we present a new thread-parallel edge and face swapping algorithm for two and three dimensional meshes using OpenMP for shared memory architectures. We show how removing the conflicts from the reconfiguration procedure by applying a vertex locking strategy can result in a near linear speed-up with parallel efficiency of close to one on two threads and 70% with 24 threads on shared-memory processors. Finally, we derive a parallel mesh generation and refinement module for shared memory architectures based on pre-existing serial modules by implementing Chernikov and Chrisochoides' parallel insertion algorithm along with the two above tools. Experiments show a worst case parallel efficiency of 50% for parallel refinement with 24 threads.

An Efficient ELLAM Implementation for Modeling Solute Transport in Fractured Porous Media

The goal of this study is to introduce an adaptation of the Eulerian-Lagrangian localized adjoint method (ELLAM) for the simulation of mass transport in fractured porous media, and to evaluate the performance of ELLAM in such a case. The fractures are represented explicitly using the discrete fracture model. The velocity field was calculated using the mixed hybrid finite element method. A sound ELLAM implementation is developed to address numerical artifacts (spurious oscillations and numerical dispersion) arising from the presence of fractures. The efficiency of the developed ELLAM implementation was further improved by taking advantage of the parallel computing on shared memory architecture for the tasks related to particles tracking and linear system resolving. The performance of ELLAM was tested by comparing its results with the Eulerian discontinuous Galerkin method based on several benchmark problems dealing with different fracture configurations. The results highlight the robustness and accuracy of ELLAM, as it allows the use of large time steps, and overcomes the Courant-Friedrichs-Lewy (CFL) restriction. The outcome also shows that ELLAM is more efficient when fracture density is increased.

Rapid Calculation of Max-Min Fair Rates for Multi-Commodity Flows in Fat-Tree Networks

Max-min fairness is often used in the performance modeling of interconnection networks. Existing methods to compute max-min fair rates for multi-commodity flows have high complexity and are computationally infeasible for large networks. In this work, we show that by considering topological features, this problem can be solved efficiently for the fat-tree topology that is widely used in data centers and high performance compute clusters. Several efficient new algorithms are developed for this problem, including a parallel algorithm that can take advantage of multi-core and shared-memory architectures. Using these algorithms, we demonstrate that it is possible to find the max-min fair rate allocation for multi-commodity flows in fat-tree networks that support tens of thousands of nodes. We evaluate the run-time performance of the proposed algorithms and show improvement in orders of magnitude over the previously best known method. We further demonstrate a new application of max-min fair rate allocation that is only computationally feasible using our new algorithms.

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system improves its efficiency and its flexibility thanks to their programmability, but increases the design complexity. The design flows indeed have to be composed of several steps to fill the gap between the starting solution, which is usually a reference sequential implementation, and the final heterogeneous solution which includes custom hardware accelerators. Among these steps, there are the analysis of the application to identify the functionalities that gain advantages in execution on hardware and the generation of their implementations by means of Hardware Description Languages. Generating these descriptions for a software developer can be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). With respect to other embedded systems scenarios, the aerospace systems introduce further constraints that have to be taken into account during the design of these heterogeneous systems. In this type of systems explicit data transfers to and from FPGAs are preferred to the adoption of a shared memory architecture. The first approach indeed potentially improves the predictability of the produced solutions, but the sizes of all the data transferred to and from any devices must be known at design time. Identifying the sizes in presence of complex C applications which use pointers can be a not so easy task. In this paper, a semi-automatic design flow based on the integration of an aerospace design flow, an application analysis technique, and High Level Synthesis methodologies is presented. The initial reference application is analyzed to identify which are the sizes of the data exchanged among the different components of the application. Next, starting from the high level specification and from the results of this analysis, High Level Synthesis techniques are applied to automatically produce the hardware accelerators.

2018 Outlook: The Emerging Web and Information Sciences

Computer’s annual Outlook issue highlights several information-becomes-knowledge paradigms, the comeback of shared-memory architecture (this time with scale-up victories), and how ubiquitous computing has finally found its OS. We also review the changes to the magazine’s editorial board and content lineup.

A 2-D FINITE VOLUME NAVIER-STOKES SOLVER FOR SUPERSONIC FLOWS

Two-dimensional compressible Navier-Stokes equations consist of continuity, momentum and energy equations. These coupled equations must be solved simultaneously. A finite volume based in house solver is developed in C++. The solver is able to solve steady, unsteady, inviscid and viscous compressible flows. It uses Van Leer’s Flux Vector Splitting Scheme. It has local time stepping feature for the acceleration of convergence and can run parallel on computers with shared memory architecture. The solver is designed to adapt alternative schemes for better accuracy and computing efficiency. In order to check the accuracy and code implementation, various supersonic benchmark problems are visited. The problems are steady inviscid double wedge, steady viscous flow over a cylinder, unsteady inviscid Sod’s problem and unsteady inviscid forward facing step flow. The obtained results are compared with those available in literature. The comparisons show that the results are promising.

Parallelization Strategy for Elementary Morphological Operators on Graphs: Distance-Based Algorithms and Implementation on Multicore Shared-Memory Architecture

This article focuses on the (unweighted) graph-based mathematical morphology operators presented in [J. Cousty et al, Morphological filtering on graphs , CVIU 2013]. These operators depend on a size parameter that specifies the number of iterations of elementary dilations/erosions. Thus, the associated running times increase with the size parameter, the algorithms running in O(λ.n) time, where n is the size of the underlying graph and λ is the size parameter. In this article, we present distance maps that allow us to recover (by thresholding) all considered dilations and erosions. The algorithms based on distance maps allow the operators to be computed with a single linear O(n) time iteration, without any dependence to the size parameter. Then, we investigate a parallelization strategy to compute these distance maps. The idea is to build iteratively the successive level-sets of the distance maps, each level set being traversed in parallel. Under some reasonable assumptions about the graph and sets to be dilated, our parallel algorithm runs in O(n/p + K log 2 p) where n, p, and K are the size of the graph, the number of available processors, and the number of distinct level-sets of the distance map, respectively. Then, implementations of the proposed algorithm on a shared-memory multicore architecture are described and assessed on datasets of 45 images and 6 textured 3-dimensional meshes, showing a reduction of the processing time by a factor up to 55 over the previously available implementations on a 8 core architecture.

Automated Synthesis of Comprehensive Memory Model Litmus Test Suites

The memory consistency model is a fundamental part of any shared memory architecture or programming model. Modern weak memory models are notoriously difficult to define and to implement correctly. Most real-world programming languages, compilers, and (micro)architectures therefore rely heavily on black-box testing methodologies. The success of such techniques requires that the suite of litmus tests used to perform the testing be comprehensive--it should ideally stress all obscure corner cases of the model and of its implementation. Most litmus test suites today are generated from some combination of manual effort and randomization; however, the complex and subtle nature of contemporary memory models means that manual effort is both error-prone and subject to incomplete coverage. This paper presents a methodology for synthesizing comprehensive litmus test suites directly from a memory model specification. By construction, these suites contain all tests satisfying a minimality criterion: that no synchronization mechanism in the test can be weakened without causing new behaviors to become observable. We formalize this notion using the Alloy modeling language, and we apply it to a number of existing and newly-proposed memory models. Our results show not only that this synthesis technique can automatically reproduce all manually-generated tests from existing suites, but also that it discovers new tests that are not as well studied.

Automated Synthesis of Comprehensive Memory Model Litmus Test Suites

The memory consistency model is a fundamental part of any shared memory architecture or programming model. Modern weak memory models are notoriously difficult to define and to implement correctly. Most real-world programming languages, compilers, and (micro)architectures therefore rely heavily on black-box testing methodologies. The success of such techniques requires that the suite of litmus tests used to perform the testing be comprehensive--it should ideally stress all obscure corner cases of the model and of its implementation. Most litmus test suites today are generated from some combination of manual effort and randomization; however, the complex and subtle nature of contemporary memory models means that manual effort is both error-prone and subject to incomplete coverage. This paper presents a methodology for synthesizing comprehensive litmus test suites directly from a memory model specification. By construction, these suites contain all tests satisfying a minimality criterion: that no synchronization mechanism in the test can be weakened without causing new behaviors to become observable. We formalize this notion using the Alloy modeling language, and we apply it to a number of existing and newly-proposed memory models. Our results show not only that this synthesis technique can automatically reproduce all manually-generated tests from existing suites, but also that it discovers new tests that are not as well studied.

Scalable shared-memory architecture to solve the Knapsack 0/1 problem

Dynamic Programming (DP) is used to solve combinatorial optimization problems and constitutes one of the 13 High Performance Computing (HPC) patterns. DP suffers from irregular, data-dependent memory accesses that deteriorates performance. The Knapsack 0/1 belongs to the simplest DP algorithms which is called Serial Monadic and has been treated in software with cache-efficient algorithms as well as parallel threads, OpenMP or MPI.In this paper we propose a shared memory, parametrizable architecture to compute the DP matrix for the Knapsack 0/1. Our system has a parallel runtime of Θ(mC/q) for a knapsack of capacity C with m items and q operators. Using additional off-chip space and DMA transfers it can solve knapsacks of any size. The architecture is implemented on the ZYNQ-7020 System On Chip (SoC) that contains a dual-core ARM plus Artix FPGA fabric. Under such architecture we make use of 64-bit High Performance ports for off-chip transfers and asymmetric 32-bit write/64-bit read BRAMs to minimize data exchange times. We also exploit computation synchronization to minimize BRAM address propagation and reduce routing congestion. We present results for a base system with 70 Processing Elements (PEs) capable of solving problems with a maximum item weight ωmax=1024. For more complex instances we configure the architecture with 58 PEs and ωmax=6144, where a single BRAM is shared among 13 computing units. We thus solve problems with 6 × bigger weights than previous works, attain a 16 × speed-up versus an optimized software on an Intel Xeon E5 and get the highest efficiency per core versus other architectures. We achieve between 2.4−3.3× acceleration versus previous FPGA solutions.