Shared Cache Research Articles

Performance of tightly-coupled systems with shared cache

Shared cache under an effective management policy can yield a hit ratio higher than that for private cache, because of the fact that shared space in the cache could be divided among the processors according to their needs, and also, only single copies of shared blocks are stored in the cache. The effective total system cache size is thus larger for shared cache than for a private cache system. This paper assumes set associative memory mapping among cache and interleaved main memory. Least Recently Used (LRU) replacement technique is utilized in case of a miss and a relation for maximum throughput of the system is developed.

Multi-level shared caching techniques for scalability in VMP-M/C

The problem of building a scalable shared memory multiprocessor can be reduced to that of building a scalable memory hierarchy, assuming interprocessor communication is handled by the memory system. In this paper, we describe the VMP-MC design, a distributed parallel multi-computer based on the VMP multiprocessor design, that is intended to provide a set of building blocks for configuring machines from one to several thousand processors. VMP-MC uses a memory hierarchy based on shared caches, ranging from on-chip caches to board-level caches connected by busses to, at the bottom, a high-speed fiber optic ring. In addition to describing the building block components of this architecture, we identify the key performance issues associated with the design and provide performance evaluation of these issues using trace-drive simulation and measurements from the VMP. This work was sponsored in part by the Defense Advanced Research Projects Agency under Contract N00014-88-K-0619.

Shared cache multiprocessing with pack computers

A typical cache accesses a block, then returns a selected word. In a pack computer design, the cache accesses and returns a block to the computer. The computer selects the word from the block and also retains blocks for reuse. The retained blocks constitute a software cache.Separate block wide caches for instructions, read data, and write data provide enough bandwidth for several pack computers to execute several instructions per cache cycle time.The concept of a pack (bundle of information) is used to bridge part of the conceptual gap between blocks and high level languages.The pack computer design has parallel issue of instructions and has vector operations.

Performance of shared cache for parallel-pipelined computer systems

Shared-cache memory organizations for parallel-pipelined multiple instruction stream processors avoid the cache coherence problem of private caches by sharing single copies of common blocks. A shared cache may have a higher hit ratio, but suffers performance degradation due to access conflicts. Effective shared cache organizations are proposed which retain the cache coherency advantage and which have very low access conflict even with very high request rates. Analytic expressions for performance based on a Markov model have been found for several important cases. Performance of shared cache organizations and design tradeoffs are discussed.

Shared Cache for Multiple-Stream Computer Systems

Cache memory organization for parallel-pipelined multiprocessor systems is evaluated. Private caches have a cache coherence problem. A shared cache avoids this problem and can attain a higher hit ratio due to sharing of single copies of common blocks and dynamic allocation of cache space among the processes. However, a shared cache suffers performance degradation due to access conflicts.

PUMPS Architecture for Pattern Analysis and Image Database Management

The PUMPS architecture consists of P task processing units (TPU) which share a pool of special peripheral processors, VLSI functional units, and a common two-dimensional shared memory (SM) via a block transfer oriented interconnection network. A shared cache is provided between the TPU's and SM for efficient MIMD interprocessor communication. The SM is also connected via a backend database management network (BDMN) with distributed control to the file memories, which are disk-based database storage devices.

Processor allocation strategies for multiprocessor database machines

In this paper four alternative strategies for assigning processors to queries in multiprocessor database machines are described and evaluated. The results demonstrate that SIMD database machines are indeed a poor design when their performance is compared with that of the three MIMD strategies presented. Also introduced is the application of data-flow machine techniques to the processing of relational algebra queries. A strategy that employs data-flow techniques is shown to be superior to the other strategies described by several experiments. Furthermore, if the data-flow query processing strategy is employed, the results indicate that a two-level storage hierarchy (in which relations are paged between a shared data cache and mass storage) does not have a significant impact on performance.