Shallow Trench Isolation Technology Research Articles

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

The narrow-width W effect of metal-oxide-semiconductor field-effect transistors (MOSFETs) with shallow trench isolation technology has been widely reported. The factor of most concern is the edge width Δw affecting the electrical characteristics of the MOSFETs. In this letter, the negative variation value of Δw, as explained in the content, was derived from 65-nm node p-channel MOSFETs (pMOSFETs). To verify the validity of Δw, the pMOSFETs were stressed by channel-hot-carrier stress conditions. According to the experimental results, the device parameter degradation, i.e., the threshold voltage VTH, was obviously dominated by |Δw|/W, and the degradation of the narrow-width device was also increased for the wide width.

Shallow Trench Isolation Stress Effect on NMOS Transistor Leakage, SRAM Standby Current and VCCMIN

Three key process steps in shallow trench isolation (STI) technology: STI liner oxide, STI to AA step height, and annealing temperature. Their impacts on NMOS devices leakage, SRAM standby current and Vccmin have been studied. MOSFET transistors off state current (Ioff) and body current (IB) were measured at varied length of diffusion (LOD) for STI stress effect analysis. For low power NMOSFET transistors, IB is seen to be the main part of Ioff and has a strong correlation to the processes that modulates STI stress. The experiment results show that the STI stress level can be much reduced by decreasing STI oxide RTA temperature and liner ox thickness, hence leading to lower IB and SRAM standby current. It is also demonstrated that SRAM Vccmin can be improved ~10% by STI stress reduction.

Effect of Wet Treatment on Stability of Spin-On Dielectrics for STI Gap-Filling in Nanoscale Memory

As a design rule of memory devices is scaled down to sub-100 nm, shallow trench isolation (STI) technology is faced with gap-filling problem in case of CVD oxide and O3-TEOS oxide processes. To overcome the gap-filling problem, a perhydropolysilazane (PHPS) based spin-on dielectric (SOD) has been implemented for nanoscale devices because of self-planarization and excellent gap-filling property [1]. However, the stability of the SOD has been concerned about because it has relatively softer and more porous than conventional HDP oxide. In this paper, we report the effect of wet oxidant treatment on the stability of the SOD for STI gap-filling.

Low-k dielectrics for trench isolation in nanoscaled complementary metal oxide semiconductor imagers

In this article the authors propose a novel T-shaped shallow-trench isolation (STI) technology including an unfilled floating void STI. The structure aims to reduce the dark current in complementary metal oxide semiconductor active-pixel sensor technology and is optimized with respect to the size of the depletion region surrounding the STI, also accounting for the fringe electric field and the leakage current. Simulations indicate that a large air void positioned far from the bottom and top of the T-shaped trench improves performance.

T-shaped shallow trench isolation with unfilled floating void

In this paper we propose a novel T-shaped shallow trench isolation technology including an unfilled floating void (VSTI). The structure aims to reduce the dark current in CMOS active pixel sensor technology and is optimized with respect to the size of the depletion region surrounding the STI, also accounting for the leakage current.Simulations outline that a large air void positioned far from the bottom and the top of the T-shaped trench improves performances.

Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

For PMOS (p-channel metal–oxide–semiconductor) transistors isolated by shallow trench isolation (STI) technology, reverse narrow width effect (RNWE) was observed for large gate lengths such that the magnitude of the threshold voltage becomes smaller when the channel width decreases. However, PMOS transistors with small gate lengths show up a strong anomalous narrow width effect such that the magnitude of the threshold voltage becomes larger when the channel width decreases. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic transient enhanced diffusion (TED) due to Si interstitials generated by the deep boron source/drain (S/D) implant towards the gate/STI edge.

Study of shallow trench isolation technology with a poly-Si sidewall buffer layer

Shallow trench isolation (STI) technology with a poly-Si buffer layer at the trench sidewall has been studied. At the densification temperature of 950 °C, for the samples without using a poly-Si buffer layer, the resulting junction shows a leakage of about 700 nA cm−2 for a diode area of 100 × 100 µm2, primarily due to large peripheral junction leakage. The large leakage is ascribed to the defect generation caused by a thermally induced stress near the trench sidewall. The usage of a poly-Si buffer layer in the trench sidewall is found to significantly improve the junction characteristics. As a result, when a 40 nm poly-Si buffer layer is sandwiched between the Si substrate and the trench-fill silicon oxide, the resultant junctions show a leakage of only about 8 nA cm−2. This result may reflect the considerably reduced thermally induced stress near the trench sidewall. Furthermore, at the densification temperature of 1100 °C, the usage of a poly-Si buffer layer can help to achieve excellent junctions with a leakage smaller than 5 nA cm−2 for a diode area of 100 × 100 µm2.

Alternative Optimization Techniques for Shallow Trench Isolation and Replacement Gate Technology Chemical Mechanical Planarization

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.

Efficient waveguide-integrated tunnel junction detectors at 1.6 μm

Near-infrared detectors based on metal-insulator-metal tunnel junctions integrated with planarized silicon nanowire waveguides are presented, which we believe to be the first of their kind. The junction is coupled to the waveguide via a thin-film metal antenna feeding a plasmonic travelling wave structure that includes the tunnel junction. These devices are inherently broadband; the design presented here operates throughout the 1500-1700 nm region. Careful design of the antenna and travelling wave region substantially eliminates losses due to poor mode matching and RC rolloff, allowing efficient operation. The antennas are made from multilayer stacks of gold and nickel, and the active devices are Ni-NiO-Ni edge junctions. The waveguides are made via shallow trench isolation technology, resulting in a planar oxide surface with the waveguides buried a few nanometres beneath.The antennas are fabricated using directional deposition through a suspended Ge shadow mask, using a single level of electron-beam lithography. The waveguides are patterned with conventional 248-nm optical lithography and reactive-ion etching, then planarized using shallow-trench isolation technology. We also present measurements showing overall quantum efficiencies of 6% (responsivity 0.08 A/W at 1.605 mum), thus demonstrating that the previously very low overall quantum efficiencies reported for antenna-coupled tunnel junction devices are due to poor electromagnetic coupling and poor choices of antenna metal, not to any inherent limitations of the technology.

Shallow Trench Isolation Top Corner Rounding Using Si Soft Etching Following Diluted Hydrofluorine Solution

Shallow Trench Isolation (STI) technology is important for realizing high-speed and high-packing-density complementary metal oxide semiconductor very large scale integrated (CMOS-VLSI) technologies. To obtain top corner rounding in STI, a new process was evaluated. This technique utilizes Si soft etching by O2+CF4 plasma following pad oxide shift in dilute hydrofluorine (HF) solution after STI formation, which effectively suppresses subthreshold slope (hump) for n- and p-channel devices even when 4 V of substrate bias is applied. This technique also does not cause top corner rounding (TCR) imbalance between narrow and wide spaces caused by the conventional sidewall generation technique in pad nitride etching. This new STI formation method markedly improves STI top corner rounding. As a result, it has been found that this technique is very effective for sub-0.18 µm STI formation.

Prevention of active area shrinkage using polysilicon stepped shallow trench isolation technology

Polysilicon stepped shallow trench isolation (PS-STI) using an Si3N4/Poly-Si/SiO2 stacked mask is proposed for 0.14 µm and beyond. The PS-STI profile has a poly-Si step length and a protrusion in the trench sidewall after PS-STI etching. The poly-Si is oxidised to form a thin liner oxide, and then a small bird's beak is grown. With this step, the penetration of the small bird's beak into the active area is prevented, increasing the active area and giving better process margins. Because of the increased active area due to the step length oxidation, the reduced contact resistance results in an increased drain current.

A Novel T-Shaped Shallow Trench Isolation Technology

This paper describes a novel T-shaped shallow trench isolation (STI) technology, which has the same effective isolation length with conventional STI but significantly reduced aspect ratio. The T-shaped STI is formed using 2-step trench etches. After the formation of the 1st trench of a relatively low aspect ratio, oxide spacer is formed inside the trench sidewall. And the 2nd trench is made to ensure an effective isolation length. When T-shaped STI is filled with undoped silicate glass (USG) and high density plasma (HDP) oxide, the mouth of 2nd trench is closed by the overhang of filling materials so that the effective aspect ratio of T-shaped STI can be lowered. We evaluated the electrical characteristics of T-shaped STI. Also, we performed simulation of the stress distribution and the junction profile. T-shaped STI has shown comparable characteristics to conventional STI and no electrical or physical degradation was found. We have adopted this technology to 512 Mbit flash memory (0.5 µm cell pitch) and obtained excellent structural and electrical properties. In addition, we obtained the excellent gap filling ability even for the 1 Gbit flash memory (0.34 µm cell pitch) and beyond.

Plasma etch-back planarization coupled to chemical mechanical polishing for sub 0.18 μm shallow trench isolation technology

A new plasma etch-back planarization technique is presented with countermasking to preplanarize shallow trench isolation (STI) substrates before chemical mechanical polishing (CMP). A preplanarization step is necessary since CMP alone cannot provide effective planarization for sub 0.18 technology due to the dishing effect. The preplanarization step uses the principle of two layer planarization technique which consists of spin coating a first photoresist layer, using a countermask for the lithographic step, flowing and curing the resist blocks in STI topographies, spin coating a second photoresist layer to planarize the residual topography, and transferring the final flat surface into the substrate using conventional plasma etch back. In difference with previous techniques, we used a special mask with oversizing and exclusion of all STI critical dimensions smaller than 1.55 μm, the zones with the smaller STI dimensions being masked using a special narrow lines grid. Such a masking strategy avoids any misalignment problem, where the resized first photoresist blocks are reflowed in STI topographies, leading to an easy planarization by the second resist layer. Additionally, the lithographic step is a noncritical step using conventional i-line resist. Using appropriate planarization model and simulation, the first layer thickness can be adjusted to get an effectively planarized topography. The final surface is then transferred into the oxide substrate using the plasma etch-back technique. Various gas mixtures were tested using LAM 4520 plasma etching equipment. The (Ar/CF4/O2) gas mixture was observed to fulfill etch-back requirements with better performance. Equality of etch rate in resist and in oxide can be adjusted by the O2/CF4 gas ratio. A design of experiment was used to determine the optimum conditions of plasma transfer of the planarized profile into the substrate. Finally, the preplanarized wafer is polished by CMP, resulting in an effectively planarized topography with residual topography smaller than 50 nm. The technique is a noncritical lithographic technique scaleable for technologies below 0.18 μm.

An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication

In this paper, a 0.3-/spl mu/m BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 /spl mu/m/spl times/1.0 /spl mu/m. This technology includes high f/sub max/ of 37 GHz at the low collector current of 300 /spl mu/A and high BV/sub ceo/ of 10 V NPN transistor, CMOS with L/sub eff/=0.3 /spl mu/m, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C/sub jc/ can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f/sub max/ at the low current region and high BV/sub ceo/ concurrently. These features will contribute to the development of high-performance BiCMOS LSI's for various mixed analog/digital applications.

A modified multi-chemical spray cleaning process for post shallow trench isolation chemical mechanical polishing cleaning application

Chemical mechanical planarization (CMP) has become widely accepted for the formation of device interconnect structures. Shallow trench isolation technology (STI) utilizes CMP and has been applied to deep-sub-micron processes. Poly Si, CVD Si or SiO2 can be grown or deposited in the trench and planarized by a CMP process. However, the typical wafer surface is contaminated with slurry particles and metallic impurities after the CMP process. The silica particles may damage the VLSI patterns and the metallic impurities can induce many crystal defects in Si wafers during the following furnace processing. Therefore, the post CMP clean is a very important step for the STI process. However, the wafer for poly-Si surface is hydrophobic, SiO2 surface is hydrophilic and Si film is very easy to charge up. Thus, the defect can be difficult to remove by a conventional cleaning technique. In this study, we propose the use of a modified multi-chemicals spray cleaning process for post STI CMP cleaning. We used a modified and heated ammonia/peroxide mix (APM) clean with an ammonia pre-soak and an HF step to etch a thin layer for the removal of trapped metallic ions which can be followed by a hydrochloric/peroxide mix (HPM) clean process to assist in the removal of metallic ions.

Integration of unit processes in a shallow trench isolation module for a 0.25 μm complementary metal–oxide semiconductor technology

This article presents a study of the issues in integrating the pattern, fill, planarization, and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 μm complementary metal–oxide semiconductor technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data are presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.

Effects of underlying films on the chemical-mechanical polishing for shallow trench isolation technology

The effects of underlying films on the chemical-mechanical polishing (CMP) removal rate have been studied and characterized. A model for the underlying film mechanical properties such as hardness and Young's modulus, relating to the polishing removal rate was proposed. In addition, a modified shallow trench isolation (STI) process with a thin nitride overcoat has been suggested to eliminate the dishing and oxide remaining on nitride issues. Furthermore, in order to minimize the residual particles and metallic contamination, a modified multi-chemical spray-cleaning process provided for the post-STI CMP cleaning was also studied.

A Novel Shallow Trench Isolation Technique

Shallow-trench isolation processes which involve refilling using deposition of oxide and polysilicon were investigated. Our results show that the oxide-filled shallow-trench isolation technology based on chemical-mechanical polishing (CMP) is difficult to control and results in poor uniformity. Use of this technology also involves in the dishing effect in wide field regions. However, shallow-trench isolation technology using a masking nitride layer, polysilicon refill, the CMP process with high etch selectivity, and local oxidation of polysilicon is easily implemented and absolutely field oxide encroachment (bird's beak) free. Although the CMP process results in the dishing effect in wide field regions, the local oxidation of polysilicon can reduce the amount of dishing. The polysilicon-filled shallow-trench isolation process can also achieve excellent uniformity across 6-inch diameter silicon wafers due to the high etching selectivity of polysilicon to chemical-vapor-deposited (CVD) oxide and SiN. Moreover, the n+/p junction leakage current of polysilicon-filled shallow trenches is comparable to that of oxide-filled shallow trenches. This simple and easily controllable process is a very promising candidate for shallow trench isolation.