Shallow Trench Isolation Etch Research Articles

Process optimization for shallow trench isolation etch using computational models

The critical dimensions of advanced semiconductor manufacturing processes have decreased to a few tens of nanometers while the aspect ratios have increased beyond 100. The performance of plasma etch patterning processes as well as the cost and time of the development cycle are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a computational patterning software, ProETCH®, has been developed with rigorous physics and advanced algorithms for modeling the etch patterning process, with the featured capabilities in calibrating the reaction mechanisms and optimizing the etch process. A shallow trench isolation etch process using self-aligned double patterning was investigated. A reaction mechanism of silicon etch by Ar/Cl2 plasma was developed to address the surface reactions, and a plasma hypermodel was introduced to correlate process operating conditions to plasma parameters at the wafer surface. The parameters of the reaction mechanism and the plasma hypermodel were calibrated with experimental data obtained from cross-sectional scanning electron microscope (XSEM) images. The calibrated model is used to identify the different fundamental pathways that contribute to the observed profile metrics in XSEMs. The model was then used for process development and optimization by solving the forward and inverse problems. In the forward problem, the model is used to predict the etching profile at different process conditions. Predictions for both interpolation conditions (process parameters within the range used for developing the model) and extrapolation conditions (process parameters outside of the range used for developing the model) agree well with the experimental data with the root mean square error less than 4 nm (1 nm resolution used for the mesh). In the inverse problem, the developed model is used to search for process conditions (e.g., values of bias power and pressure), which could result in desirable profiles. The solutions to the inverse problem demonstrate a degeneracy in process space of the etching process for a given target profile.

Highly repeatable dry etch corner rounding solution for 0.11 μm shallow trench isolation

A highly repeatable dry etch corner rounding solution for 0.11 μm shallow trench isolation (STI) without increasing additional process steps was proposed. It is mentioned for the first time that the two-step silicon nitride over etching method is used in the STI etching to get the corner rounding effect, in which the gas combination is CF4 + CH2F2. The top rounding can be achieved by properly adjusting the proportion of two-step etching gas. The STI prepared by this method has a perfect top rounding morphology in both dense and isolate areas. The subsequent TEM images show that the thickness of gate oxide at the thinnest part increased from 40 to 52 A, an increase of 30%. The results of the gate oxide integrity test confirmed that the value of breakdown voltage is greatly improved by using the new etching methods regardless of n-MOS or p-MOS. In terms of the breakdown voltage, the improvement level of n-MOS is higher than that of p-MOS. The breakdown voltage of n-MOS is increased by 10% and that of p-MOS is increased by 7%. With the further reduction of semiconductor size, the increase in gate oxide thickness in corner of STI is very important for the improvement of device reliability and performance.

Fabrication technique of the Si0.5Ge0.5 Fin for the high mobility channel FinFET device

In this paper, a fabrication technique of Si0.5Ge0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si0.5Ge0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si0.5Ge0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si0.5Ge0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si0.5Ge0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si0.5Ge0.5 Fin is already oxidized and SiGeOx has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si0.5Ge0.5 Fin loss with sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.

Correlation Study of Bulk Si Stress and Lithography Defects Using Polarized Stress Imager

Polarized Stress Imaging is an excellent method for monitoring bulk stress distribution in silicon wafers. In this study, the correlation of bulk Si stress and lithography defects are shown using Semilab’s Polarized Stress Imager (PSI) system. 300 mm diameter samples with 7 nm advanced node FinFET devices were investigated with PSI optical imaging metrology tool and AMAT’s UVision wafer inspection tool. Two sets of samples were analyzed after shallow trench isolation etch and after gate etch. Results show that stress imaging can detect process deviations that lead to high defectivity and may have uses in failure analysis to pinpoint root causes of failures.

Investigation on the formation technique of SiGe Fin for the high mobility channel FinFET device

In this work, SiGe Fin formation technique using shallow trench isolation (STI) first or STI last strategy for the high mobility channel FinFET device is systematically investigated. A 20 nm width and 35 nm height high crystalline quality of the Si0.7Ge0.3 Fin formation for STI first scheme is demonstrated by utilizing a new developed Si Fin etching, Si Fin recess and SiGe selective epitaxial growth process. For the STI last strategy, a novel chemical mechanical planarization (CMP) treated three-layer SiGe strain relaxed buffer (SRB) is successfully fabricated and a 50 nm high crystal quality and atomically smooth surface Si0.5Ge0.5 layer on this SRB is attained. Moreover, a spike annealing is employed to avoid the Si0.5Ge0.5 Fin oxidation during STI densification with an acceptable STI etching rate. However, both a spike annealing and a lower temperature of traditional furnace at 850 °C or 750 °C suffer micro-trench issue during the Fin reveal process. Therefore, a new developed process, named as STI recess first, is developed to resolve both thermal instability and micro-trench issue at the same time. A minor Si0.5Ge0.5 Fin loss with a sharp Si0.7Ge0.3 SRB/Si0.5Ge0.5 interfaces for STI last scheme is realized by utilizing this new developed STI recess first process.

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top corner rounding is important to devices performance. AA top corner rounding techniques include STI etch, linear oxidation , H2 annealing and wet oxide pull back (PB). However, conventional STI etch will caused AA facet and need to additional thermal in linear oxidation or H2 annealing processes. Wet oxide PB is easily to control the pad oxide etching amount and reach desired AA top corner top rounding radius.In this study, different pad oxide PB amount by Hydrogen Fluoride (HF) with corner rounding correlation were shown. At high pad oxide PB amount, additional hydrogen peroxide (H2O2) with dilute HF can optimize the AA top corner profile and enlarge the corner radius. Sharp AA corners profile caused gate oxide formation thickness thinning let strong electrical filed at AA corner. In wafer acceptable test had brought about double hump effect in I-V characteristics and inverse narrow width effect. Pad oxide PB following STI Etch is used by HF to let the silicon top corner be exposed and beneficial for increasing AA top corner rounding radius of liner oxidation process. This study gives some course to improve the silicon corner profile and AA top corner radius. After STI etch process, different wet etch amount were used for pad oxide PB from pad nitride by 0.49% HF process time adjustment. Different wet oxide PB amount were split for corner radius comparison. As oxide PB amount increased from 0nm to 5nm the corner radius can be improved, and the best radius showed at PB 5nm. When oxide PB amount add to 7.5nm, the corner radius became worse slightly. The radius of PB 10nm is even worse and close to without oxide PB process. This result suspected that AA corner profile might be changed in wet oxide PB process. When oxide PB amount increase, oxide etch rate might decrease and exposed silicon corner be continually damaged by HF erosion. The silicon damage of PB 5nm is slight and can be recovered after linear oxidation thermal process. At PB 7.5nm the AA corner “stepped” profile was observed. It can explain while the PB amount >5nm the corner rounding radius decrease. Because the “stepped” profile caused the corner split two curvatures then the radius decrease. The “stepped” profile of PB amount >7.5nm still be find after linear oxidation. To reduce the AA top corner “stepped” profile, the post-HF treatment’s AA silicon exposed in following APM process. The AA top corner and silicon sidewall which with APM treatment is clipping suspect H2O2 oxidize silicon and NH4OH consume the oxide caused. This profile made the region of exposed silicon to be deficient and pointed in AA geometry of silicon corner. The pointed AA top corner profile is unhelpful for corner rounding radius improvement, so the key factor of AA top rounding profile is corner silicon loss controller. In order to reduce the corner silicon loss amount, using H2O2 to replace the APM and dilute HF concentration to do oxide PB. This optimistic experience will be expected lower the exposed corner silicon consumption and corner rounding radius improvement. According oxide PB amount 5nm and 7.5nm comparison in 0.49%HF, the corner radius reduced 0.1nm when the PB increased. Nonetheless, HF concentration changed from 0.49% to 0.1% and H2O2 addition, the corner radius can be improved 0.3nm and 0.7nm. This result proved that the corner silicon profile of PB >5nm will be damaged in concentrated HF wet etch. Change to dilute HF concentration will reduce corner silicon loss and enable to recover corner silicon which with “stepped” profile by additional H2O2 treatment. As the higher oxide PB amount the pad oxide PB rate will become lower cause that without oxide protected corner silicon will be damaged and result in “stepped” profile. Nevertheless, using dilute HF can lower corner silicon loss and reduce the silicon erosion which without oxide protected. Additional H2O2 treatment introduced the rounding and smooth profile. The relationship between pad oxide PB and AA top corner rounding is established in STI process. The AA top corner radius of oxide PB amount 5nm can be improved 2.6nm compare to without PB process. When oxide PB amount >5nm the corner radius is decreased. The decreasing corner radius come from higher oxide PB amount that without oxide protected corner silicon will be damaged. This phenomenon result in “stepped” profile with difference curvature and corner radius decreasing. Dilute HF with H2O2 treatment is demonstrated that it is beneficial to reduce and recover the corner damaged. Figure 1

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top cornerrounding is important to device performance. AA top cornerrounding techniques include STI etch [1], linear oxidation [2], H2annealing [3] and wet oxide pull back (PB). However,conventional STI etch will caused AA facet and needs additionalthermal in liner oxidation or H2 annealing processes. Wet oxide PBeasily controls the pad oxide etching amount and reaches thedesired AA top corner top rounding radius. In this study, differentpad oxide PB was achieved by hydrogen fluoride (HF) etching andcorrelated with corner rounding. For high pad oxide PB, additionalhydrogen peroxide (H2O2) with dilute HF (DHF) can optimize theAA top corner profile and enlarge the corner radius.

Model Quality Evaluation in Semiconductor Manufacturing Process With EWMA Run-to-Run Control

Exponentially weighted moving average run-to-run (EWMA-RtR) controller is frequently adopted in semiconductor manufacturing process. As a model-based control method, the performance of EWMA-RtR controller greatly depends on the process model quality, hence the process model-plant mismatch is an important factor influencing the control performance. In this paper, a model quality evaluation method for semiconductor manufacturing process with EWMA-RtR control is proposed without introducing any external excitation. The white noise sequences are first obtained from the routine closed-loop data by an orthogonal projection method and a disturbance model is estimated from the output error by recursive extended least square method. A model quality variable is then defined and calculated using the disturbance model and the output error. The model evaluation index is proposed using the ratio between the variance of the estimated white noise and that of the model quality variable. The effectiveness of the proposed method is demonstrated by a simulated chemical mechanical polishing process and a shallow trench isolation etch process based on industrial data.

Wet Chemical Etching Behavior Investigation for CMOS Shallow Trench Isolation (STI) Shape Control

Shallow trench isolation (STI) divot shape control is always one of most key logic process in semiconductor fabrication. Conventional wet chemical treatment easily cause deep divot and result in transistor kink effect of drain current (Id) v.s. gate voltage (Vg) relation curve. Gas phase chemical etching method can reduce divot level around 55% compared with conventional wet batch type dilute HF (DHF) etching. This study indicated that divot formation is highly correlated to etching surface geometry, chemical boundary layer thickness and chemical flow speed. By etching method selection and parameter adjustment, divot can be controlled in logic process.Shallow trench isolation (STI) divot profile usually affects MOS transistor electrical properties, such as drain current (Id) versus gate voltage (Vg) double hump curve (kink effect), due to parasitic transistor formation. Slightly STI divot is acceptable in most logic processes. However, it is observed that under the same STI SiO2 etching amount, gas phase chemical etching divot level is around 55% reduced by comparing with conventional batch type wet chemical (dilute HF) etching, showed in Figure 1.Divot levels difference between gas phase etching method and conventional wet etching method was observed. In this study, some key points had been defined, showed as Figure 2, to monitor STI SiO2 loss phenomenon during different etching methods. Point a is STI vertical top SiO2 loss amount; point b is STI sidewall top SiO2 loss; point c is STI sidewall bottom SiO2 loss; b/a is the SiO2 loss ratio of STI sidewall top to vertical top; c/a is the SiO2 loss ratio of STI sidewall bottom to vertical top.To figure out the behavior of STI SiO2 loss, single wafer spin wet etching method was added and split three spin speed conditions as 800rpm, 1500rpm and 2200rpm. Figure 3. showed TEM images of STI etching by gas phase, batch type DHF and spin type DHF process. Table 1 and Figure 4 showed a, b, c values of above etching methods.Normally, isotropic etching rate will be affected by geometry effect. Larger etched surface exposed results in higher etching rate due to different surrounding reactant amount, showed as Figure 5. That means the ratio (c/a) of STI vertical top SiO2 loss to sidewall bottom SiO2 loss should be less than 1 theoretically, which had been observed in batch DHF etching method.However, from Figure 4, spin type DHF etching method showed c/a ratio larger than 1. Based on Bernoulli's effect, reactant (HF2 -) at STI top will be dragged down to the STI sidewall bottom area due to higher DHF flow speed in small tunnel area. Higher flow speed induced thinner boundary layer, and sufficient reactant makes STI sidewall bottom etching rate increasing. The mechanism showed as Figure 6. By increasing spin speed from 800rpm to 2200rpm, c/a ratio changed from 1.13 to 1.03, approaching to batch type value 0.91. Higher spin speed also increased DHF flow speed at STI top and minimized the flow speed difference between STI top and sidewall bottom.For gas phase chemical etching, HF and NH3 mixing gas is usually used for SiO2 etching, and byproduct (NH4)2SiF6 is generated and deposit on SiO2 surface which will interfere following reactants diffusing toward SiO2 surface for further etching reaction. As byproduct thickness increasing, finally, etching stop due to no reactants touching fresh SiO2 surface. The mechanism showed in Figure 7. c/a ratio less than 1 can also be found in gas phase etching method, and much less than 1 due to the combination effect of geometry and byproduct interfering.Table 2 showed each etching method characteristics and merit/ demerit, gas phase etching has no water mark issue and has well divot control capability. Both batch type and spin type DHF etching methods have water mark risk, but spin type DHF etching method can prevent wafer surface particle redeposit.Spin type wet etching process becomes mainstream in semiconductor foundry due to excellent particle defect performance, but higher chemical flow speed inducing higher etching rate in STI SiO2 small tunnel and causing deeper divot, although increasing spin speed can minimized the divot level. Gas phase type etching has intrinsic diffusion barrier of etching byproduct. Combining gas phase and DHF etching methods for all STI SiO2 etching processes can get expected final divot profile or only using gas phase etching method can achieve excellent divot control capability in logic 28nm generation or more advanced MOSFET fabrication processes. Figure 1

Process Optimization on Self-Aligned Double Patterned Fin Formation

As the feature size of integrated circuit (IC) keeps shrinking, self-aligned double patterning (SADP) has been widely used in 14nm technology node and beyond.[1] In SADP Fin etch,the precise pattern transfer is critical for the robust device performance. However, compared with single patterning scheme, SADP poses more challenges from the point of view of even/odd issue, RIE-lag loading and line width roughness (LWR) control.In this work,we delivered the overall solution by introducing the bias pulsing plasma etch and mixed mode pulsing(MMP) concept in mandrel and shallow trench isolation (STI) to address the rigorous loading control [2] between dense and isolated patterns, the synchronous pulsing scheme to form the spacer with almost flat spacer top, thus benefiting the even/odd performance in SADP fin etch. Besides,we also investigated the effects of plasma ribbon beam[3], chemical down-stream etch (CDE) and high conductance on LWR improvement, respectively. Rigorous loading control at dense and isolated patterns is important to ensure the robust device performance.This is especially true at sub20nm technology node. In SADP Fin etch, the dense-isolated loading (including CD, depth and sidewall angle) mainly comes from mandrel etch and STI etch process. As is well known, etch by-product deposition mode behaves quite differently between dense and isolated area. In traditional continuous wave (CW) plasma, it’s quite hard to tackle such notorious loading for its inherent high Te induced ionization. While, the bias pulsing plasma paves the way to alleviate such toggled loading for less bombardment during the bias-off period could reduce the etch by-product formation to some extent.Moreover, MMP plasma enables precise etch process control by repeatedly resetting each phase to initial state which could eliminate most of process induced loading accumulation.Based on the above learning, we induced MMP concept in STI etch process and successfully developed a well-controlled loading performance on Fin (shown in Fig1). In SADP Fin etch,both spacer top profile and mandrel performance are extremely critical to final even/odd performance. On one hand, the mandrel performance could result in the difference of depth and line edge roughness (LER) between mandrel space and spacer space as schematically shown in Fig 2a. Such even/odd distribution could finally introduce the huge variation of the effective Fin height. Among three different mandrel materials, we found such even/odd issue could be improved by means of mandrel material selection.On the other hand, traditional spacer etch process usually delivers the undesired spacer shoulder loss(schematically shown in Fig2a).Such asymmetric spacer height pattern could be directly transferred to Fin formation and easily induce the asymmetric stress distribution on Fin, which could potentially lead to Fin distortion. Here, we resorted to the synchronous pulsing scheme to reshape the spacer top profile without the excessive loss of spacer height. LWR has aroused much attention as CMOS is being scaled down to FinFET. Both high frequency LWR and low frequency LWR have to be addressed at mandrel definition as the LWR of ALD spacer strongly depend on mandrel LWR. We leveraged plasma ribbon beam to improve low-frequency LWR of photo resist and did achieve the remarkable improvement. However, the substrate damage and photo resist loss need special method such as synchronous pulsing scheme to reduce photo resist loss during etch process. Besides, CDE was used to improve high-frequency LWR at mandrel and Fin. However, the result is quite different between them. 30% LWR reduction could be seen on Fin while it does NOT work on mandrel at all. This might come from the material difference or insufficient CD loss. Last but not least, mandrel etch itself could deliver better high LWR performance with high conductance and special photo resist treatment. ACKNOWLEDGMENT This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type).

Study on processing step uniformity tuning during FET fabrication and sensor wafer response as a function of chuck temperature adjustment

The effect of chuck temperature adjustment on critical dimension uniformity was studied for the shallow trench isolation etch process by introducing a temperature gradient in a multi-temperature-zone electrostatic chuck. It is shown that the initial radial critical dimension non-uniformity can be improved by a gradual temperature adjustment of the electrostatic chuck and results in the target specification values of uniformity, 3σ ≤ 1.5 nm, for a critical dimension of about 35 nm. Both temperature and RF sensor wafers were used to analyze the impact of an electrostatic chuck temperature gradient on process uniformity by utilizing their unique in situ spatial and temporal mapping capabilities. Thus, the across-wafer thermal sensitivity of the critical dimension was estimated for dense structures: a temperature change of 1 °C leads to a critical dimension change of ∼0.7 nm. The RF sensor wafer was also shown to have a clear response of RF current uniformity to the electrostatic chuck temperature gradient that suggests there could be other phenomena affecting critical dimension uniformity besides temperature itself. The pure temperature contribution to critical dimension change was found to be less than 0.3 nm/°C for the temperature range studied. Finally, a possible mechanism of critical dimension tuning is discussed and an assessment of each separate etch step’s sensitivity to the electrostatic chuck temperature gradient is performed.

Advanced STI Etch Process Development on NMC Etcher

As the dimensions of semiconductor devices continuously shrink, it becomes critical and challenging to control process loading in reactive ion etch (RIE) to ensure precise patterning and to avoid performance degradation among different patterns. Basically, the loading effect in RIE comes from its inherent local environment discrepancy around different patterns such as dense and isolated (ISO) patterns. Some part of the etch process loading can be reduced by adopting proper pattern schemes. Shallow trench isolation (STI) etch process demonstrated the hard mask (HM) approach could significantly improve the depth loading by reducing the aspect ratio as thinner HM can be used. While other methods such as etch process optimization are needed to further reduce the process loading. In this paper, we systematically investigated the profile (sidewall angle) and depth loadings among dense and semi-isolated lines in STI etch from the point of view of various process parameters such as pressure, power, and chemical gases. It was found that proper chemical gases were critical for loading control on sidewall angle and depth. Besides, bias power was also found to drastically impact the loading performance. Based on the above learning, an STI etch process was successfully demonstrated on an NMC 612B etcher with both WAT and yield verification.

Feature profile evolution during shallow trench isolation etching in chlorine-based plasmas. III. The effect of oxygen addition

The effect of oxygen addition to chlorine plasma during shallow trench isolation etching is quantified in this work. Specifically, the electron density and the electron temperature in an electron cyclotron resonance reactor were characterized by a Langmuir probe and were found to remain relatively constant upon O2 addition. The silicon etching rates were found to increase with the square root of the ion energy, suggesting the etching reaction is limited by the momentum transfer from ions to the surface. A relatively small amount of oxygen addition (<10%) to the chlorine plasma simultaneously changes the reactor wall conditions and surface kinetics, since oxygen becomes actively involved in the surface reactions. The change in the chamber wall conditions and surface kinetics leads to the change in both the amount of etch products and the etched feature profile. The incorporation of oxygen on the surface results in a significant change of the etched surface morphology and its composition. This work suggests a small amount of O2 addition to Cl2 plasmas in shallow trench isolation etching changes the etching behavior primarily through modifying the kinetics on etched surfaces. A multiscale etch model consisting of translating mixed layer and Monte Carlo modules for bulk and feature scale etching, respectively, was successfully applied to this case, demonstrating good agreement with the experimental results.

Feature profile evolution during shallow trench isolation etch in chlorine-based plasmas. II. Coupling reactor and feature scale models

A two-dimensional numerical fluid model was developed to investigate the effects of reactor design on the radial profiles of plasma species, namely, etch products and positive ions, during shallow trench isolation etching in Cl2∕O2∕Ar inductively coupled plasmas. Specifically, the dual-coil and dual gas-feed designs of the reactor were examined. The former parameter was determined to be effective in tailoring the radial ion flux profile at pressures higher than 20mT, while the latter parameter was shown to alter the etch product transport in the convection-dominant flow regime. Coupling of the reactor scale model to a feature scale model allowed investigation of minor center to edge variations in the etched feature profile. This hybrid model suggests that the general radial decrease in the etch depth seen from a set of design of experiments is caused by an inherent decrease in the spatial distribution of chlorine radicals. In addition, the increase in the silicon sidewall angle from center to edge can be qualitatively explained by the radial profile of the etch products.

Feature profile evolution during shallow trench isolation etch in chlorine-based plasmas. I. Feature scale modeling

The authors developed a cellular based Monte Carlo (MC) feature scale model capable of direct coupling to the dominant plasma species ratios from a reactor scale model in order to simulate the profile evolution of shallow trench isolation etch in chlorine-based plasmas and its variation from the center to the edge of the wafer. Carefully planned experiments along with scanning electron microscopy (SEM) were used to calibrate the MC model, where one to two plasma parameters were systematically varied. Simulated feature profiles were found to agree well with experimental observations, capturing details such as microtrenching, faceting, tapering, and bowing. The particle counts used to achieve these fits agreed well with those estimated from SEM, corroborating the chemistry and physics used in the feature scale model. In addition, the feature scale model uses a novel surface representation that eliminates the artificial flux fluctuations originating from the discrete cells used in the simulation and enables a much more precise calculation of the surface normal, which dictates the trajectory of reflected species.

A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology

A new STI (shallow trench isolation) with automatic top corner rounding (ATCR) to improve 90 nm CMOS narrow width device performance has been studied in detail. Experimental results show that the ATCR mitigates the inverse narrow width effect, and increases the driving current (Idsat) by 8% together in a unit process step, thus getting easy process control and cost down benefits, which cannot be achieved through conventional methods. Additionally, the ATCR attained a better trench depth uniformity, and thus a wider process window (20–50 s) than that of the conventional method. Furthermore, the technique does not degrade the gate oxide integrity and junction leakage current; thus the developed ATCR STI technique is more suitable for 90 nm and beyond narrow width CMOS technologies.

Recursive Least Squares Estimation for Run-to-Run Control With Metrology Delay and Its Application to STI Etch Process

Run-to-run (RtR) control technology has received tremendous interest in semiconductor manufacturing. Exponentially weighted moving average (EWMA), double-EWMA, and internal model control (IMC) filters are recognized methods for online RtR estimation. In this paper, we consider recursive least squares (RLS) as an alternative for online estimation and RtR control. The relationship between EWMA-type and RLS-type estimates is analyzed and verified with simulations. Because measurement delay is almost inevitable in semiconductor manufacturing, we discuss and compare the performance of EWMA, RtR-IMC, and RLS controllers in handling measurement delay and measurement noise for processes with a deterministic drift. An ad hoc solution is proposed to handle measurement delay for processes with time-varying drifts. The results are illustrated through several simulations and a shallow trench isolation (STI) etch process as an industrial example.