Seysen's Algorithm Research Articles

Low-Latency Lattice Reduction Based on Dual-Basis Updates for High-Dimensional MIMO Streams

Lattice reduction (LR) techniques have been widely adopted to enhance the detection performance with low additional complexity in spatial multiplexed multiple-input multiple-output (MIMO) systems. However, in large MIMO systems, the required number of iterations and the corresponding latency and complexity of the existing LR algorithms increase exponentially. In this brief, we propose a low-latency LR method based on Seysen's algorithm (SA) for high-dimensional MIMO systems. The proposed algorithm introduces dual-index selection and simultaneously updates two basis pairs without the recalculation of metrics to reduce the latency and complexity. Additionally, it introduces a reduced candidate set to decrease the computational complexity and memory usage. The numerical results demonstrate that the proposed LR-aided linear detector outperforms the conventional Lenstra-Lenstra-Lovász algorithm. Furthermore, the performance of the proposed method is comparable to that of SA; it achieves reductions of 40% and 12.5% in the number of iterations and computational complexity, respectively. The proposed 65-nm CMOS implementation achieves an overall latency of 196 ns and a throughput of 25.5 M matrix/s with a clock frequency of 357.1 MHz for $8 \times 8$ MIMO systems.

Lattice reduction aided pre-processor for large scale MIMO detection

Linear detectors such as Minimum Mean Square Error (MMSE), Zero Forcing are applied for large scale MIMO detection because of their low computational cost, but has the least performance. In this paper, improvement in the performance of lattice Reduction aided- linear detectors for large scale MIMO is analyzed. Lattice reduction is performed using Seysen's Algorithm (SA). SA finds the reduced basis with minimum number of iterations compared to the commonly used Lenstra, Lenstra, and Lovász (LLL) algorithm. Also, SA based reduction of channel matrix, outperforms the existing LLL algorithm based reduction for sub optimal linear detectors in terms of bit error rate (BER) and computational complexity. The simplified VLSI architecture of SA is implemented in hardware using 45 nm technology

A Seysen's algorithm–based incremental lattice reduction

AbstractLattice reduction (LR)–aided detections have attracted great attention in the symbol detection of multiple‐input–multiple‐output communication, especially for systems with larger scale antennas. Recently, the Lenstra‐Lenstra‐Lovász (LLL)–based incremental LR (ILR) algorithms have been proposed to employ an early termination to jointly conduct the LR and retrieve the symbol based on a partial successive interference cancellation (SIC) detection, which induces a significant performance improvement. In this paper, we propose to apply the Seysen's algorithm (SA) to the ILR. After providing the feasibility analysis, two novel SA involved algorithms are introduced and studied. In particular, a new sorted QR decomposition‐based SA algorithm is proposed and tested as it plays a key role in the SIC detection. Subsequently, a novel SA‐based ILR scheme is further developed and investigated. By simulations, we show that the proposed approach outperforms conventional LLL‐based ILR in various aspects, while only a marginal increment in the complexity, restricted to medium signal‐to‐noise‐ratio regions, is observed.

A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

In this paper, a VLSI implementation of a complete MIMO channel equalization ASIC based on lattice reduction-aided linear detection is presented. The architecture performs preprocessing steps at channel rate and low-complexity linear data detection at symbol rate. Preprocessing is based on Seysen's algorithm for lattice reduction. We present algorithmic improvements of the lattice reduction preprocessing in terms of area and throughput of the VLSI implementation with minor impact on the error-rate. Due to the low-complexity implementation of the lattice reduction-aided data detection stage, our architecture is able to achieve very low power in typical packet-based MIMO wireless data transmission scenarios. The final 90 nm CMOS ASIC achieves an energy efficiency for the detection of 24 pJ/bit at a throughput of 720 Mbps with near-optimal error-rate performance.

Design of Lattice Reduction Algorithms for Linear-Precoded MIMO System

In this letter, the design of lattice reduction (LR) algorithms specialized for improving the performance of a linear-precoded MIMO system is investigated. Conventionally, the lattice reduction algorithm required in such system is performed mostly by either the Lenstra-Lenstra-Lovasz (LLL) or the Seysen's algorithm (SA), which is designed to search for shorter or nearly-orthogonal bases of a lattice. In this letter, we show that additional performance gain can be further obtained by taking the mean-square-error (MSE) of the considered MIMO system into account. The computational complexity and the error rate achieved by the proposed algorithm is quantified and compared with the LLL and SA via numerical simulations.

A New Lattice Reduction Algorithm for LR-Aided MIMO Linear Detection

Lattice reduction (LR) has recently emerged as a promising technique for improving the performance of suboptimal multiple-input-multiple-output (MIMO) detectors. For LR-aided MIMO detection, the Lenstra-Lenstra-Lovasz (LLL) and Seysen's algorithm (SA) have been considered almost exclusively to date. In this paper, we introduced a new LR algorithm for LR-aided linear detection (LD). In contrast to the LLL and SA, which are targeted to search for bases with relatively short basis vectors, the proposed algorithm has been designed to improve the minimum Euclidean distance of the LR-aided linear detector, thus exhibiting improved error rate at high SNR. The error-rate performance of the proposed algorithm as well as the required complexity has been demonstrated through extensive computer simulations.

Designing Low-Complexity Detectors Based on Seysen's Algorithm

Lattice reduction (LR) has been applied to linear equalizers and decision feedback equalizers to improve their performance. Recently, Seysen's algorithm (SA) has been proposed as an alternative LR method to the well-documented LLL algorithm. In this paper, we first provide a tree-search implementation method of SA which enables flexible performance-complexity trade-offs. Based on this tree structure, SA-aided hard-output and soft-output detectors are proposed to enhance performance. The diversity and complexity of the proposed methods are also studied. Thorough comparisons of SA and other LR algorithms are provided. Our analysis of complexity and numerical simulations provide insights that are useful to system designers.

An analysis of Seysen's lattice reduction algorithm

Lattice reduction (LR) techniques have been adopted to improve the performance and/or reduce the complexity in communications and cryptography. So far, the LLL algorithm has been considered almost exclusively for LR. In this paper, we focus on Seysen's algorithm to perform LR. We show that for a lattice in two dimensions, Seysen's algorithm gives the same reduced basis as the well-known Gaussian reduction algorithm (up to signs). Furthermore, we prove that the Seysen's metric is upper bounded for lattices in two dimensions after LR with Seysen's algorithm. Finally, we relate Seysen's metric to the orthogonality deficiency for general cases.