Seven-level Diode-clamped Inverter Research Articles

Efficiency and Power Loss Distribution in a High-Frequency, Seven-Level Diode-Clamped Inverter

The paper presents efficiency and power loss analysis in a high-frequency, seven-level diode-clamped inverter (7LDCB). The inverter is composed of four-level (4L) diode-clamped branches based on MOSFET transistors and Si Schottky diodes. The range of DC-link voltages enables the operation of the inverter in connection with a single-phase power grid. The tested inverter can be controlled using various modulation concepts that affect its parameters, but also energy losses. Carrier-based modulation, which may be useful in a few applications, is compared to selective modulation based on the state machine (SM-based) algorithm. The article demonstrates the efficiency level of the inverter as well as the influence of the modulation method and switching frequency on the efficiency and loss distribution in semiconductor devices. The article also shows the hardware implementation of a complex modulation algorithm based on selective switching states used to maintain voltage balance on three DC-link capacitors. Redundant switching states allow the generation of the same voltage but with the use of a selected DC-link capacitor. This makes it possible to balance the DC-link voltage with the load current. The article presents experimental results, which show the advantage of using the modulation method with selective switching states. First, it allows for equalizing the loading of DC-link capacitors. The second advantage is a more uniform distribution of losses in semiconductor components.

Optimal HSE-PWM based on genetic algorithm for seven levels diode clamped multilevel inverter

In this paper, the control of seven level diode clamped inverter with selective harmonic elimination (SHE) pulse width modulation (PWM) technique based on genetic algorithm (GA) has been developed. In standard SHE-PWM, the seven level inverters allow the elimination of only two low order harmonics. To improve the total harmonic distortion (THD), and without any modification to the inverter structure, five low order harmonics can be eliminated by suitably adding holes in the stairecase voltage leg. Furtheremore, a hole distribution in agreement with the sin function shape is proposed. For this, a real-coded genetic algorithm is applied under the standard constraints with a proposed cost function minimization that allow a better near sin function reshape of the output voltage leg. This GA computation allow to determine the switching angles for a seven-level diode clamped inverter to produce the required fundamental voltage and to eliminate undesirable harmonics. This developed procedure can eliminate a desired number of low harmonics and is only restricted by the maximal switching frequency of the power switches. The results of the suggested method are compared to the conventional SHE-PWM involved with a seven level staircase wave. They reveal that the developed method is a very effective one for optimal harmonic elimination technique.

Seven-level diode clamped inverter fed IPMSM drive for high power applications

In recent years, multilevel inverters have become popular and widely accepted for high-power and high-voltage applications. Their performance is much superior to conventional two-level inverter as the level of the inverter increases. They produce superior quality output with less harmonic distortion. In this paper, simulation analysis of seven-level diode clamped inverter fed to interior permanent magnet synchronous motor (IPMSM) drive has been done for higher power applications. Two modulation techniques such as sinusoidal pulse width modulation (SPWM) and unified space vector pulse width modulation (USVPWM) are used. The carrier space vector pulse width modulation gives the same output reference wave as space vector pulse width modulation (SVPWM) without the actual calculation of the angle and sector location of space vector as in case of space vector modulation. The inverter output is fed to interior PMSM drive and the closed loop operation has been done using field oriented control (FOC). Speed-torque characteristics for various load conditions are studied. The output voltage and current harmonics are analysed for seven-level diode clamped inverter using SPWM and USVPWM techniques in MATLAB Simulink software.

Seven-level diode clamped inverter fed IPMSM drive for high power applications

Seven-level diode clamped inverter fed IPMSM drive for high power applications

Harmonic Optimization of Diode-clamped Multilevel Inverter Using Teaching-learning-based Optimization Algorithm

This paper proposes a harmonic elimination technique for online reducing harmonics in voltage source inverters. In the presented method, in order to provide required fundamental voltage and eliminate specified harmonics simultaneously, the value of the switching angles are determined using a new efficient optimization algorithm named Enhanced Teaching-learning-based Optimization (ETLBO). The efficiency of the presented strategy is validated on three-phase seven-level diode-clamped inverter while other structures of multi-level inverters (MLIs) can be employed. The aim is to reduce the Total Harmonic Distortion (THD) in multilevel converter. In this paper, a new optimization algorithm named ETLBO has been successfully implemented to achieve optimal switching angles in order to harmonic elimination in MLIs. A three-phase seven-level diode-clamped MLI has been selected as a test case to validate the effectiveness of the proposed method. The simulation results demonstrated the ETLBO method not only is in preference to the Genetic Algorithm and Particle Swarm Optimization for including no user-defined parameter and simple implementation, but also for providing higher quality solutions. Moreover, in order to verify the superiority of the ETLBO algorithm over conventional methods for harmonic elimination, the Newton-Raphson (NR) method was implemented to find optimal switching angles. The results obtained by the NR method compared with those of the ETLBO and the superiority of the ETLBO in terms of the both computational time and the resulted %THD was concluded. As a whole, the results show that the ETLBO algorithm is expected to become widespread in power systems where on-line updating harmonics is needed since it provide accurate and high-quality solution in extremely short time.