Seven-level Cascaded H-bridge Research Articles

Reduced-Capacitance Thin-Film H-Bridge Multilevel STATCOM Control Utilizing an Analytic Filtering Scheme

In this paper, an analytic capacitor voltage filtering scheme for a cascaded H-bridge (CHB) multilevel converter-based static synchronous compensator (STATCOM) is proposed. The scheme is able to filter out a low-frequency ripple of any magnitude and introduces a negligible delay to the control system. Therefore, it facilitates using high-reliability film capacitors with low capacitance instead of the conventional electrolytic capacitors. The proposed analytic filtering scheme is implemented and verified on a single-phase seven-level CHB multilevel converter-based STATCOM. The parameters' sensitivity evaluation is provided to demonstrate practicability of the proposed scheme. Simulation and experimental results are provided to compare the performance of the proposed filtering scheme with the performance of the most commonly used second-order filter-based approach to demonstrate its effectiveness.

Fault-Tolerant Control of Cascaded H-Bridge Converters Using Double Zero-Sequence Voltage Injection and DC Voltage Optimization

Cascaded H-Bridge (CHB) converters can be directly connected to medium-voltage grids without using transformers and they possess the advantages of large capacity and low harmonics. They are significant tools for providing grid connections in large-capacity renewable energy systems. However, the reliability of a grid-connected CHB converter can be seriously influenced by the number of power switching devices that exist in the structure. This paper proposes a fault-tolerant control strategy based on double zero-sequence voltage injection and DC voltage optimization to improve the reliability of star-connected CHB converters after one or more power units have been bypassed. By injecting double zero-sequence voltages into each phase cluster, the DC voltages of the healthy units can be rapidly balanced after the faulty units are bypassed. In addition, optimizing the DC voltage increases the number of faulty units that can be tolerated and improves the reliability of the converter. Simulations and experimental results are shown for a seven-level three-phase CHB converter to validate the efficiency and feasibility of this strategy.

A voltage balancing strategy with extended operating region for cascaded H-bridge converters

In this paper, a generalized switching technique for cascaded H -bridge (CHB) converters is proposed. To take advantage of both low- and high-frequency modulation techniques, a hybrid modulation method is utilized. The proposed technique employs the low-frequency switching for voltage balancing of the dc-link capacitors, and the high-frequency sinusoidal pulse-width modulation switching for shaping the input ac current. Using the proposed technique, the stable operating region of CHB converters is extended. The proposed technique is capable of maintaining the dc voltages balanced even under critical operating conditions in which the load of one H-bridge cell is removed. The validity and effectiveness of the proposed method is confirmed by several simulation and experimental tests on a seven-level CHB rectifier.

Selective harmonic mitigation‐pulse‐width modulation technique with variable DC‐link voltages in single and three‐phase cascaded H‐bridge inverters

There are different modulation techniques that can be used in medium-voltage and high-power electronic converters, but a few of them provide high efficiency and satisfy power quality requirements. This study presents a modified selective harmonic mitigation pulse-width modulation (SHM-PWM) technique which employs variable DC-link voltages as a degree of freedom in cascaded H-bridge (CHB) inverters. This degree of freedom increases the range of acceptable modulation indices, reduces the number of switching transitions and increases the number of harmonics that can be removed in selective harmonic elimination (SHE) (or SHM) techniques. Hence, in addition to efficiency improvement, a huge number of harmonics can be mitigated in AC side of the converter. Using this approach, triplen harmonics can be restricted to standard limits, in single-phase inverters. In addition, the proposed SHM-PWM approach employs the least number of switching transitions in a fundamental period to limit the specific number of harmonics compared to the alternative SHE or SHM techniques. In this study, the requirements of two well-known grid codes EN 50160 and CIGRE WG 36-05 are well satisfied and the validity of proposed method is verified by several simulations and experiments on a seven-level CHB inverter in single-phase and three-phase operating modes.

Simplified space vector modulation technique for seven‐level cascaded H‐bridge inverter

A simplified space vector modulation (SVM) technique is proposed for the seven-level cascaded H-bridge (CHB) inverter. It is based on decomposing the seven-level space vector hexagon into a number of two-level space vector hexagons. The presented technique significantly reduces the calculation time and efforts involved in the SVM of a seven-level inverter; without any loss in the output voltage magnitude or increase in the total harmonic distortion content. A further simplified technique is also presented in this study, which significantly reduces the complexity and effort involved in the seven-level SVM. Simulation results for the seven-level CHB inverter using the proposed techniques are presented. The results are compared with results using sinusoidal pulse-width modulation (PWM) and third harmonic injection PWM to prove the validity of the proposed techniques. The proposed technique is perfectly general and can be applied to all types of multilevel inverters and extended to higher level inverters.

A Complete Harmonic Elimination Approach to DC Link Voltage Balancing for a Cascaded Multilevel Rectifier

This paper presents a complete method that is used to balance dc link voltages in a cascaded H-Bridge (CHB) multilevel rectifier. Recently, such converters have been the subject of extensive research due to their suitability for high-power applications. One requirement in using a multilevel active rectifier at high levels of power is to limit the switching losses by reducing the switching frequency to a minimum. Another requirement for these converters is to ensure that individual dc link capacitor voltages for each cell of the converter are always balanced to ensure controllability and to limit stress on the converter cells. This paper presents a complete method in solving both of these problems using a selective-harmonic-elimination pulsewidth-modulation scheme. The scheme utilizes a simple controller to track each cell dc link capacitor voltage magnitude and accordingly biases the power flowing into each cell to ensure that the voltages across each cell capacitor converge. This is the case even when the loads attached to the individual cells are not balanced. The theory is supported by both simulated results from Saber and by experimental results from a seven-level CHB single-phase multilevel rectifier.