Design Of Server Research Articles

I/O Printed Circuit Board Assemblies; Recent Learning in Mechanical Stress Analysis, Verification Testing, and Post-test Analysis Techniques and Results

Recent high-end server designs have included new Input / Output (I/O) printed circuit board (PCB) assemblies consisting of a variety of form factors, electronic design layouts, and packaging assembly characteristics. To insure the required functional and reliability aspects are established and maintained, new mechanical analysis and verification testing techniques have been recently devised. A description of the design application set, the analysis tools and techniques applied, and the verification testing completed, including the associated measurement techniques as well as post-testing analysis methods and results are presented. Also included are the recent PCB raw card characterization efforts whose results have been applied as material property inputs to the analysis to improve analytical-to-empirical correlation. Included within the application set are both the use of custom designed cards as well as industry standard, original equipment manufacturer (OEM) cards that are packaged within custom enclosures. Given packaged and unpackaged (i.e., as installed in a higher-level rack system assembly) fragility testing requirements, new analysis techniques exploiting the capabilities of LS-DYNA have been used to provide a predictive means to support both initial as well as iterative design levels. In addition, these analysis results are also used to identify locations for measurement sensor placement employed during mechanical verification testing. Thermal shock and mechanical shock and vibration verification testing details and results are provided describing the conditions applied to simulate assembly shipping conditions, both as packaged as well as in situ to the higher-level of assembly. Included with this is a discussion with respect to post-test analysis techniques and results, including the use of both microscopic cross-section analysis as well as dye-pry assessments. Concluding, continued and future activities are described as “best practices” for the application of this methodology as part of the end-to-end development process.

EBG-Based Common-Mode Microstrip and Stripline Filters: Experimental Investigation of Performances and Crosstalk

The aim of this study is to analyze from a modeling and experimental point of view the filter effectiveness and the crosstalk among signal traces crossing the same common-mode filter based on electromagnetic bandgap structures in a modern server design configurations. Both microstrips and striplines are considered in the study, detailing the differences among them in the design step as well as in filter geometry and response. Simulation models and experimental setups are carefully described, and the numerical and measurement results are compared and discussed.

DjiNN and Tonic

As applications such as Apple Siri, Google Now, Microsoft Cortana, and Amazon Echo continue to gain traction, web-service companies are adopting large deep neural networks (DNN) for machine learning challenges such as image processing, speech recognition, natural language processing, among others. A number of open questions arise as to the design of a server platform specialized for DNN and how modern warehouse scale computers (WSCs) should be outfitted to provide DNN as a service for these applications. In this paper, we present DjiNN , an open infrastructure for DNN as a service in WSCs, and Tonic Suite , a suite of 7 end-to-end applications that span image, speech, and language processing. We use DjiNN to design a high throughput DNN system based on massive GPU server designs and provide insights as to the varying characteristics across applications. After studying the throughput, bandwidth, and power properties of DjiNN and Tonic Suite, we investigate several design points for future WSC architectures. We investigate the total cost of ownership implications of having a WSC with a disaggregated GPU pool versus a WSC composed of homogeneous integrated GPU servers. We improve DNN throughput by over 120x for all but one application (40x for Facial Recognition) on an NVIDIA K40 GPU. On a GPU server composed of 8 NVIDIA K40s, we achieve near-linear scaling (around 1000x throughput improvement) for 3 of the 7 applications. Through our analysis, we also find that GPU-enabled WSCs improve total cost of ownership over CPU-only designs by 4-20x, depending on the composition of the workload

Measuring Disclosure Risk and Data Utility for Flexible Table Generators

Abstract Statistical agencies are making increased use of the internet to disseminate census tabular outputs through web-based flexible table-generating servers that allow users to define and generate their own tables. The key questions in the development of these servers are: (1) what data should be used to generate the tables, and (2) what statistical disclosure control (SDC) method should be applied. To generate flexible tables, the server has to be able to measure the disclosure risk in the final output table, apply the SDC method and then iteratively reassess the disclosure risk. SDC methods may be applied either to the underlying data used to generate the tables and/or to the final output table that is generated from original data. Besides assessing disclosure risk, the server should provide a measure of data utility by comparing the perturbed table to the original table. In this article, we examine aspects of the design and development of a flexible table-generating server for census tables and demonstrate a disclosure risk-data utility analysis for comparing SDC methods. We propose measures for disclosure risk and data utility that are based on information theory.

English

This paper is about the application of data acquisition systems in industrial requirements for real time execution of events with industrial process control and automation. The main core of the system is an embedded hardware running a scaled-down version of Linux: a popular choice of operating system for embedded applications. On -line embedded web server is a challenging part of many embedded and real time data acquisition and control system applications. The World Wide Web is a global system of interconnected computer networks that use the standard Internet Protocol Suite (TCP/IP) to serve billion of users worldwide and allows the user to interface many real time embedded applications like data acquisition, Industrial automations and safety measures etc., In this project we approached towards the design and development of on-line Interactive Data Acquisition and Control System (IDACS) using ARM based embedded web server. It can be a network, intelligent and digital distributed control system. Single chip IDACS method improves the processing capability of a system and overcomes the problem of poor real time and reliability. This system uses ARM9 Processor portability with Linux operating system it makes the system which handling various processes based on multi tasking and reliable scheduling mechanisms. A novel approach is introduced to minimize the operational costs while operating with a large amount of data. The system is demonstrated to be suitable for different embedded applications by attaching several real-time modules through appropriate interfaces. The embedded web server technology is the combination of embedded device and Internet technology, through this embedded web server user can access their equipments remotely. The equipment mentioned here could be home appliances and factory devices. This paper is focused on realization of TCP/IP suite and user development platform for this embedded web server. The embedded web server design includes a complete web server with TCP/IP support and Ethernet interface. Web pages are written by Hyper text markup language (HTML).

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

To advance datacenter capabilities beyond what commodity server designs can provide, the authors designed and built a composable, reconfigurable fabric to accelerate large-scale software services. Each instantiation of the fabric consists of a 6 x 8 2D torus of high-end field-programmable gate arrays (FPGAs) embedded into a half-rack of 48 servers. The authors deployed the reconfigurable fabric in a bed of 1,632 servers and FPGAs in a production datacenter and successfully used it to accelerate the ranking portion of the Bing Web search engine by nearly a factor of two.

Sirius

As user demand scales for intelligent personal assistants (IPAs) such as Apple's Siri, Google's Google Now, and Microsoft's Cortana, we are approaching the computational limits of current datacenter architectures. It is an open question how future server architectures should evolve to enable this emerging class of applications, and the lack of an open-source IPA workload is an obstacle in addressing this question. In this paper, we present the design of Sirius, an open end-to-end IPA web-service application that accepts queries in the form of voice and images, and responds with natural language. We then use this workload to investigate the implications of four points in the design space of future accelerator-based server architectures spanning traditional CPUs, GPUs, manycore throughput co-processors, and FPGAs. To investigate future server designs for Sirius, we decompose Sirius into a suite of 7 benchmarks (Sirius Suite) comprising the computationally intensive bottlenecks of Sirius. We port Sirius Suite to a spectrum of accelerator platforms and use the performance and power trade-offs across these platforms to perform a total cost of ownership (TCO) analysis of various server design points. In our study, we find that accelerators are critical for the future scalability of IPA services. Our results show that GPU- and FPGA-accelerated servers improve the query latency on average by 10x and 16x. For a given throughput, GPU- and FPGA-accelerated servers can reduce the TCO of datacenters by 2.6x and 1.4x, respectively.

Sirius

As user demand scales for intelligent personal assistants (IPAs) such as Apple's Siri, Google's Google Now, and Microsoft's Cortana, we are approaching the computational limits of current datacenter architectures. It is an open question how future server architectures should evolve to enable this emerging class of applications, and the lack of an open-source IPA workload is an obstacle in addressing this question. In this paper, we present the design of Sirius, an open end-to-end IPA web-service application that accepts queries in the form of voice and images, and responds with natural language. We then use this workload to investigate the implications of four points in the design space of future accelerator-based server architectures spanning traditional CPUs, GPUs, manycore throughput co-processors, and FPGAs. To investigate future server designs for Sirius, we decompose Sirius into a suite of 7 benchmarks (Sirius Suite) comprising the computationally intensive bottlenecks of Sirius. We port Sirius Suite to a spectrum of accelerator platforms and use the performance and power trade-offs across these platforms to perform a total cost of ownership (TCO) analysis of various server design points. In our study, we find that accelerators are critical for the future scalability of IPA services. Our results show that GPU- and FPGA-accelerated servers improve the query latency on average by 10x and 16x. For a given throughput, GPU- and FPGA-accelerated servers can reduce the TCO of datacenters by 2.6x and 1.4x, respectively.

Software-Defined Cluster

The cluster architecture has played an important role in high-end computing for the past 20 years. With the advent of Internet services, big data, and cloud computing, traditional clusters face three challenges: 1) providing flexible system balance among computing, memory, and I/O capabilities; 2) reducing resource pooling overheads; and 3) addressing low performance-power efficiency. This position paper proposes a software-defined cluster (SDC) architecture to deal with these challenges. The SDC architecture inherits two features of traditional cluster: its architecture is multicomputer and it has loosely-coupled interconnect. SDC provides two new mechanisms: global I/O space (GIO) and hardware-supported native access (HNA) to remote devices. Application software can define a virtual cluster best suited to its needs from resources pools provided by a physical cluster, and traditional cluster ecosystems need no modification. We also discuss a prototype design and implementation of a 32-processor cloud server utilizing the SDC architecture.

Research on Design and Implementation of Application Server Based on Java

With the development of computer network technology, Java has a fairly extensive use of die circumference. Especially in recent years, the development of the smart phone system is also stimulated the use of the Java language. In this paper, Java server is mainly divided into two categories JSP server and Java EE servers. Java EE function which has more features than perfect JSP servers. Application server is a chief platform of Web-based application. J2EE is a standard of enterprise-scale application server. In this paper J2EE is analyzed from the point of view of software architecture and Java-based application development. Some defects of J2EE are pointed out, such as J2EE being unable to support version management and it having diverse concepts and notions due to its multi-tier architecture. Furthermore, a light weight application server—J Web Frame is developed, which overcomes some problems of J2EE.

Design of WSN Identifier Encoding Conformance Test System Based on Web

Accurate and unique sensor node identifier encoding will be an important factor to ensure the application of Wireless Sensor Network (WSN) identifier. Therefore, in order to detect the conformity of the WSN identifier encoding, the design and implementation of a WSN identifier encoding conformance test system based on web are presented. The WSN identifier encoding conformance test system consists of test method, system function, and test architecture. System function includes executable test suite (ETS) generation function, the test preparation function, the test execution function, the test response information analysis function and the test analysis function. For rapid conformance and credibility of the test system, we designed the conformance test software which consists of test server and test router. The design of test server includes man-machine interface, application service components, supporting service components and system management. The design of test router includes data communication layer management, test execution management. The implementation of test system mainly including the dataflow of test system and implementation process of test server. Verification of the test system comprises ETS verification and the test execution result verification. Additionally, the WSN identifier encoding test specifications was formulated according to the design of test system. The test results demonstrate the effectiveness of the test system by testing the sensor nodes in WSN.

Design of Graduate Employment Network SMS Platform

The paper design a new employment website, which change the previous employment website focusing only on employment information release mode, pay attention to improve students' employment ability, establish several enterprises and graduates, entrepreneurship and other. At the same time with JSP engine, Oracle established the information interactive website as the background database server; it will improve the efficiency and quality of the traditional employment information. At the same time, the paper introduces implementation of enterprise SMS platform using a GSM module, including the hardware environment, the SMS server software architecture, function and design. The scheme realizes the information exchange between students, teachers, and parents, through the practical operation, proved that the system has good practicability, solves many problems that exist in the employment information service, it has less demanding on the hardware, the realization of a simple, two times the development of convenient features.

Large Form Factor Hybrid LGA Interconnects; Recent Applications and Technical Learning

Recent high-end server design trends have continued to challenge electronic packaging engineers to design and integrate larger form factor land grid array (LGA) attached modules within their assemblies. These trends have included the application of larger, denser, organic packaged modules whose electrical performance and postencapsulation physical characteristics have been enabled by both the continued development of hybrid LGA connectors as well as new module actuation hardware designs. In this paper, we'll discuss these recent trends, including the specific technical attributes and challenges that need to be addressed to ensure a repeatable and reliable assembly design is developed. Initially, overviews of the latest connector and module design trends, including styles and physical sizes and their implications to the module's bottom surface metallurgy (BSM) flatness requirements, etc. are provided. Pursuant to this, recent system integration trending is reviewed; including both the module quantity per system assembly as well as module to module physical placements and how each of these impact printed wiring board (PWB) design (i.e., layer count, LGA site flatness, etc.) as well as the PWB assembly's solder processing characteristics (i.e., LGA pre- and post-solder attach contact co-planarity, etc.). Completing the application portion, is a description of some recent LGA actuation hardware and module external cooling apparatus designs (e.g., air-cooled heats sinks and water-cooling cold-plates and thermal interface materials (TIMs), etc.). The remaining portion of the paper is dedicated to the description of the mechanical analysis efforts completed to provide a fundamental understanding of the design's “as-assembled” attributes and a review of the associated evaluation completed to verify the integrated assembly's reliability characteristics. From the analysis methodology perspective, both the means of including each of the integrated assembly's key attributes (e.g., module mechanical construction and as encapsulated flatness, LGA contact compliance and stiffness as well as soldered contact coplanarity, TIM stiffness, actuation hardware, heat sink and cold-plate mechanical construction, etc.) and the resulting estimation of the predicted module internal TIM and hybrid-LGA's Pb-free soldered interface strains, actuation hardware stresses and LGA contact load variation are provided. Completing the discussion is a review of the variety of testing executed to validate the design's intended reliability. Included in this is a description of the test vehicle's design, the environmental stress testing conducted (i.e., mechanical pre-conditioning, accelerated thermal cycling (ATC), mixed flowing gas (MFG) and heat aging (HA), etc.) and the resulting data.

스마트워크를 위한 개방형 협업 솔루션 서버 설계

스마트워크에 대한 사회적 요구는 세계적으로 증가하고 있으며 선진국의 경우 오래전부터 스마트워크 활성화를 위한 프레임워크를 진행해 오고 있다. 국내에서도 정부주도의 스마트워크 도입을 통해 보다 효율적인 경쟁력 제고를 꾀하고 있는 실정이다. 본 논문은 다양한 스마트 환경을 통합하고 단말 간 상호연동을 제공하는 보급형 협업 솔루션을 개발하고자 한다. 기존의 PC 및 모바일 단말, 가정용 단말 등에 적용 가능한 범용 솔루션을 개발하여 직장, 외부공간, 가정을 잇는 스마트워크 공간 구축을 목표로 한다. 특히, 본 논문에서는 이동통신 플랫폼사가 보유한 협업 플랫폼 및 통화 플랫폼과 연계하여 중소기업 및 일반인을 대상으로 하는 보급형 협업솔루션을 제안하는 장점이 있다.

The Research Based on CDN Technology in Communication System Server Design

This paper designed and developed a series of Windows operating system for basic platform CDN technology, combined with the Socket of TCP/IP technology and to the network distributed database for the center. From design to achieve several aspects of instant messaging system of communication server are expounded.

A reconfigurable fabric for accelerating large-scale datacenter services

Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6x8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server, accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb SAS cables In this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system when ranking candidate documents. Under high load, the largescale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution--- or, while maintaining equivalent throughput, reduces the tail latency by 29%

Architecture Design and Cyber Security Evaluation of a Festival Management System Server

This article introduces an architecture design of a festival management system server. The design incorporates the concept of n-tier architecture and that of ‘thin’ server. The designed architecture was evaluated in view of cyber security, particularly defense-in-depth concept. The evaluation was performed to check if the features of the defense-in-depth concept according to a guideline are applied properly to the architecture. After reflecting the evaluation results, the designed architecture has become adequate for a festival management system when the high security is required for the system.

An Embedded FTP Server: Research and Implementation

Traditional File Transmission Protocol (FTP) servers are not suitable for embedded environments since these servers take complicating factors into account and consequently take a lot of memory space. Moreover, some FTP server applications even manage all file transmission by utilizing graphic user interface. However, such server is not adequate for embedded environments. When embedded system needs is more memory-efficient efficient in a resource restricted system. To cope with this problem, in this problem we conduct research on lightweight FTP server for embedded systems. And, we first summarize features of a lightweight FTP server. Then, based on the design requirements for FTP server for embedded systems, a lightweight FTP server is designed. The server adopts a command-line user interface and other advanced features, such as transmission encryption and graphic user interface, are abandoned for efficiency reasons. Last, to evaluate our design of the FTP server, several experiments are conducted and all results show that the FTP server works quite well under embedded environments. With more and more embedded systems emerging in the industry, it can be expected that the software introduced in this paper will play a more and more important role in the industry.

Integrated 3D-stacked server designs for increasing physical density of key-value stores

Key-value stores, such as Memcached, have been used to scale web services since the beginning of the Web 2.0 era. Data center real estate is expensive, and several industry experts we have spoken to have suggested that a significant portion of their data center space is devoted to key value stores. Despite its wide-spread use, there is little in the way of hardware specialization for increasing the efficiency and density of Memcached; it is currently deployed on commodity servers that contain high-end CPUs designed to extract as much instruction-level parallelism as possible. Out-of-order CPUs, however have been shown to be inefficient when running Memcached. To address Memcached efficiency issues, we propose two architectures using 3D stacking to increase data storage efficiency. Our first 3D architecture, Mercury, consists of stacks of ARM Cortex-A7 cores with 4GB of DRAM, as well as NICs. Our second architecture, Iridium, replaces DRAM with NAND Flash to improve density. We explore, through simulation, the potential efficiency benefits of running Memcached on servers that use 3D-stacking to closely integrate low-power CPUs with NICs and memory. With Mercury we demonstrate that density may be improved by 2.9X, power efficiency by 4.9X, throughput by 10X, and throughput per GB by 3.5X over a state-of-the-art server running optimized Memcached. With Iridium we show that density may be increased by 14X, power efficiency by 2.4X, and throughput by 5.2X, while still meeting latency requirements for a majority of requests.

Integrated 3D-stacked server designs for increasing physical density of key-value stores

Key-value stores, such as Memcached, have been used to scale web services since the beginning of the Web 2.0 era. Data center real estate is expensive, and several industry experts we have spoken to have suggested that a significant portion of their data center space is devoted to key value stores. Despite its wide-spread use, there is little in the way of hardware specialization for increasing the efficiency and density of Memcached; it is currently deployed on commodity servers that contain high-end CPUs designed to extract as much instruction-level parallelism as possible. Out-of-order CPUs, however have been shown to be inefficient when running Memcached. To address Memcached efficiency issues, we propose two architectures using 3D stacking to increase data storage efficiency. Our first 3D architecture, Mercury, consists of stacks of ARM Cortex-A7 cores with 4GB of DRAM, as well as NICs. Our second architecture, Iridium, replaces DRAM with NAND Flash to improve density. We explore, through simulation, the potential efficiency benefits of running Memcached on servers that use 3D-stacking to closely integrate low-power CPUs with NICs and memory. With Mercury we demonstrate that density may be improved by 2.9X, power efficiency by 4.9X, throughput by 10X, and throughput per GB by 3.5X over a state-of-the-art server running optimized Memcached. With Iridium we show that density may be increased by 14X, power efficiency by 2.4X, and throughput by 5.2X, while still meeting latency requirements for a majority of requests.