Series-parallel Type Research Articles

Realization and analysis of a new switched-capacitor coilless power supply for one-chip IC implementation

A coilless dc-dc converter using a new switched-capacitor (SC) transformer is proposed. The SC transformer consists of one voltage averaging capacitor and a capacitor string of n capacitors. In a conventional SC transformer such as a series-parallel type, the input current ripple is large and its step-up (step-down) ratio is (1/n). Therefore, attempts to reduce the current ripple by restricting the switch currents and to obtain a fractional step-up or step-down ratio by connecting SC transformers in cascade have been made. In these cases, the efficiency is decreased and the circuit configuration becomes complex. In the proposed method, (1) the ripple of the input and output currents is extremely small since the input and output ports are always connected to the taps of the capacitor string, (2) it is easy to realize any fractional transformer ratio because the taps connected to the input terminal and/or to the output one can be easily changed, and (3) the proposed circuit is suitable for IC implementation together with other signal circuits (such as a system-on-chip) since the proposed circuit has no magnetic parts (such as a coil or a transformer) and the magnetic field generation is almost absent. In this paper, (1) the circuit configuration, the operation, and the ideal equivalent circuit are described as the general case; (2) a prototype of an SC type dc-dc converter (taking n = 3 as an example) was fabricated and measured to confirm the theoretical characteristics; (3) a high power conversion efficiency (80%) and the high power density (1.4 W/cm3) were realized in the case of an SC type dc-dc converter (n = 2 as an example) implemented in a hybrid IC form. © 1998 Scripta Technica, Syst Comp Jpn, 29(12): 19–33, 1998

ARMA modeling of a room transfer function at low frequencies.

equal to the number of poles. 3. Measured impulse responses Impulse responses were measured in an experimental room, changing the reverberation time. The room was rectangular with a volume of 87 m3. The rever-beration time was set to 0.3, 0.36, 0.55, 1.6, and 2.4 s in the 500 Hz octave band by adding or removing ab-sorbing materials to or from the walls. The upper frequency of the signal bands was changed to 100, 200, 300, 400, 500, 600, 800, and 1,000 Hz. The lower frequency of the bands was fixed to 60 Hz. The sampling frequency was 2.5 times the upper frequency of the frequency band. An example of the impulse responses is shown in Fig. 1. 4. ARMA modeling of the measured impulse re-sponses The measured impulse responses were modeled by a series-parallel type ARMA model as shown in Fig. 2. The ARMA model coefficients were estimated using the RLS algorithm5) so as to minimize the error e(k) between the real echo and the estimated echo. The order of the ARMA model (P+Q) was determined such that the power of the error e(k) normalized by the power of the real echo y(k) was -40 dB. Figure 3 shows experimental results. The vertical axis represents the orders of the ARMA and the MA models that give a ratio of the error power to the real echo power of -40 dB. The horizontal axis represents the tap length of the measured impulse responses where the reverberation level drops by -40 dB. Since the order of the MA model directly corresponds to the tap length of the impulse responses, the MA model requires as many taps as the impulse response has. On the other hand, the order of the ARMA model is found to be smaller than that of the MA model, especially for the low frequency band. For example, when modeling an impulse response whose band is from 60 200 Hz for a reverberation time of 1.8 s, the MA model re-quires 600 taps, but the ARMA model requires only 240 taps. In each frequency band, when the rever-beration time is long, the ARMA model can effectively reduce the orders. These results show that the ARMA model is more effective in the low frequency band and for long reverberation times for reducing the number

An Accurate 8 Bit A/D Converter Sampling at 100 MHz

A very high-speed 8 bit A/D converter in which the sampling rate is 100 MHz has been developed. This converter is intended for application to a high-definition television (HDTV) system. The converter maintains high linearity even at high input frequencies. The basic configuration of the converter is a three-stage seriesparallel type. A digital correction system and ac coupling are used. The characteristics of the converter are as follows. At 100 MHz sampling rate, 8 bit/sample and for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 V _{p-p} (75 \omega)</tex> input operation, the linearity error is less than 1/2 LSB, DG at 30 percent 24.3 MHz subcarrier less than 1.5 percent.

An A/D Converter with 10 Bits/Sample by 20 MHz Sampling Rate

An A/D converter circuit system with a very high bit-rate has been developed. It is a series-parallel type, and the input of the last A/D stage is equivalently ac-coupled. This can be allowed by the statistical charactertstics of input signals. A prototype of this A/D converter has the following characteristics: 1) dc coupled analog input-able to accept almost all analog signals as well as television signals; 2) sampling frequency up to 20 MHz; 3) linear coding scheme with 10 bits per sample; 4) linearity error of less than one third of quantizing level; 5) differential gain and differential phase of 0.4% and 0.25°, respectively; and 6) operating temperature range of from 0° to 50°C.

Finding the MTBF of repairable systems by reduction of the reliability block diagram

Systems consisting of units with independent failures and with adequate repair facilities to initiate the repair of any unit when it fails are considered. Such systems can be assumed to be made up of independently operating units. The representation by reliability block diagrams of how successful operation of such a system is determined by the successful operation of its constituent units is well known. In the same way that reliability block diagrams can be reduced to find the reliability of a non-maintained system, the reliability block diagram of a system of independent units can be reduced to find the availability of the repairable system. Using the same reduction procedure, the MTBF of the system can be found in terms of the MTBF and availability of the individual units. The formulae for reducing the different basic connections of blocks are derived. However, the reduction procedure applies only to systems of the series-parallel type; the method of extending it to systems that would be series-parallel if some unit were replaced either by a short circuit or by an open circuit is discussed.

An extension of Hazony and Nain's synthesis procedure for n-ports

An extension of Hazony and Nain's passive reciprocal n-port network synthesis procedure to the case of passive nonreciprocal n-port networks is outlined. Generally, more than the minimum number of reactive elements is required for the realization, but the resulting network possesses a series-parallel type of structure which may be useful in certain applications. Transformers are in general required.

Optimizing simple circuitry for reliability and performance by failure mode

MANY PAPERS have been written about redundant circuits in which components can undergo either open-circuit or short-circuit failure. John von Newmann studied the problem in connection with abstract automata.1 Shannon and Moore showed that any given reliability could be achieved by using redundancy, however, as the reliability approaches 1, the number of parts involved approaches infinity.2 Other papers have been written that derive the formulas for mean time to failure and/or reliability for series-parallel and parallel-series type arrangements, that is, for n items in series and m such arrangements of n items in parallel, or n items in parallel and n such arrangements of n items in series.3,4 In applications to either ground-based equipment or microminiaturized parts such analysis is sufficient. However, there is not a true optimization until all circuits are considered. In systems with tight size, weight, and power requirements, all circuits must be considered. This paper discusses all circuits containing four components or less. Graphs are presented showing the circuit's optimizing reliability for any component reliability distribution. Then the exponential distribution is assumed, and the circuits maximizing the expected life are found. In both these optimization procedures, there will be optimal circuits which are not of the parallel-series or series-parallel type.

Magnetic Analogs of Relay Contact Networks for Logic

Two techniques are described for designing multiapertured magnetic structures capable of realizing any specific logic function. The structures are made from rectangular hysteresis loop material. The designs are derived from the corresponding relay contact network by replacing each current carrying conductor in the relay circuit with its analog in the magnetic circuit, a flux-carrying conductor, replacing the emf with a pulsed mmf; and replacing each back contact with a saturable portion of the magnetic circuit in the topological equivalent of the contact network. A flux reversal through a saturated portion may then be blocked by means of an inhibiting Current applied to a suitable winding, the current representing a logical input variable. Thus flux may be ``steered'' through the magnetic circuit in a manner analogous to the steering of current through the contact network. For planar structures the first technique may be used to obtain the analog of series-parallel and bridge type circuits; parallel circuits. It is pointed out that the analog of a relay tree can be used as a standard structure suitable for realizing any Boolean function. Representative examples of both designs are shown, and experimental data are given.

A numerical-graphical method for synthesizing switching circuits

ALTHOUGH methods for synthesizing switching circuits have been developed, the search for easily applied techniques is still receiving considerable attention. Recently, for example, a great deal of work has been done on the development of matrix methods,1 which lead to efficient nonseries-parallel circuit arrangements. Matrix methods, however, are still in the formative stage and have not as yet proved to be practical circuit-design tools. The direct application of Boolean algebra,2 on the other hand, yields circuits of the series-parallel type, which generally are not very efficient. In addition, a designer has a large number of alternative procedures available to him in the application of Boolean algebra, and can not usually ascertain beforehand the procedure which will result in the best circuit arrangement.

The effect of capacitance on the design of toroidal current-transformers

The design of high-accuracy current-transformers for operation at rated currents of less than five amperes or at frequencies higher than 50 c/s should include consideration of the effects of capacitance. The performance of transformers is shown to be dependent not only on the magnitudes of the self-capacitances of the windings and the mutual capacitance between the windings, but also upon the distribution of the capacitance between windings. With the normal method of winding a transformer layer by layer, the capacitance between windings is concentrated between the outer turns of the inner winding and the inner turns of the outer winding. This is shown to be an unsatisfactory distribution, and the performance is improved if the capacitance between windings is symmetrical and distributed as much as possible.A satisfactory distribution of capacitance between windings and also low self-capacitances are obtained by adopting a winding technique well known in radio work, in which the order of winding the turns is such that adjacent turns are as nearly as possible consecutive turns.Further improvement of the transformer performance may be obtained by increasing the thickness of insulation between windings and using insulation of low permittivity. It is shown that the thickness of this insulation may, with advantage, be about one-eighth of the mean depth of the secondary winding.Formulae are given for estimating the capacitances and leakage reactances of the transformer. It is shown that the leakage reactance of the secondary, when both windings are uniformly distributed round the core, is negative.The performance of multi-ratio transformers, especially of the tapped primary type, is necessarily less satisfactory than that of single-ratio transformers, but considerable improvements may be made by adopting an arrangement of the winding which is symmetrical with regard to the secondary for all ratios. Good winding arrangements for multi-ratio transformers with primary windings of the series-parallel type or with secondary windings of the tapped type are also suggested.

Microphone Mixers

The design of compensated microphone mixer circuits is discussed. The purpose of such circuits is to provide impedance matches for all the microphones in the circuits by means of so-called “compensating” or “building-out” resistors. General equations are obtained for the values of these resistors for multi-channel mixers of both the parallel and series-parallel type.