Serial Shift Research Articles

Buried junction and efficient carrier separation in CdSexTe1−x/CdTe solar cells

Alloying CdTe absorbers with Se is a critical advancement for the fabrication of highly efficient CdTe thin-film solar cells. Herein, the role of the Se concentration gradient in CdSexTe1−x/CdTe solar cells is stressed in addition to the decreased bandgap and passivation effect of Se. The buried graded CdSexTe1−x at the front interface of the device was stripped and analyzed by quasi in situ x-ray photoelectron spectroscopy depth profiling. A serial shift of Fermi level toward the valence band was probed as the Se concentration decreased in the graded CdSexTe1−x absorber, revealing the presence of n-type CdSexTe1−x region near the front contact. Kelvin probe force microscopy characterizations and voltage-dependent photocurrent collection analysis further confirmed the existence of a buried junction in the graded CdSexTe1−x absorber. The CdS-free CdTe solar cell with a graded CdSexTe1−x/CdTe absorber fabricated in this study showed an efficiency of 17.6%. These results indicated that the non-uniform distribution of Se introduced a built-in field in the graded CdSexTe1−x absorber and enabled efficient separation of photogenerated carriers, yielding high-performance CdTe solar cells in the absence of a conventional n-type CdS window layer. This study deepened the understanding of the performance enhancement in Se-containing CdTe solar cells and provided new ideas for further performance optimization.

Built-In Self Test (BIST) Architecture Simulation for Testing Crosstalk Effects in Array Structured Through Silicon Vias (TSV) in 3DICs

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a nanotechnology-based circuit design technology to design efficient circuits. Serial–parallel multiplier (SPM) is an efficient hardware circuit used in different applications ranging from simple arithmetic circuits, filters to complex cryptographic systems. In this work, an architecture that can be used for realizing SPM in QCA is discussed. Based on that architecture, an efficient 4-bit SPM is implemented in QCA. The proposed multiplier is also realized using efficient shift registers and adders. Parallel and serial shift registers are introduced in the circuit to store the inputs and outputs to increase the reliability of the circuit. The proposed work is the first of its kind to implement SPM with shift registers to store input and output in QCA. The proposed multiplier without shift registers is efficient and at least 66% faster compared to existing designs. The 4-bit multiplier with shift registers has 2271 cells covering an area of 7.74 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}} ^{2}$ </tex-math></inline-formula> with 25.25 clock cycle latency. To showcase, the scalability of a serial adder is also realized using the universal, scalable, and efficient clocking scheme.

Testable MUXED-D Scan Cell in Quantum-dot Cellular Technology

Quantum-dot Cellular Automata (QCA) is one of the new nanoscale technologies which proposed for future circuits. This technology has been remarkable due to its faster speed, lower size and reduction in power consumption compared to CMOS technology. Many circuits have been implemented in this technology including shift registers, they are one of the most important digital circuits for many applications. With the development of QCA technology, it is important to provide testing methods for testing these circuits.4-Bit serial shift registers designed in previous research were not capable of testing their output. In this paper, MUXED-D scan cell concept helps to detect the errors before fabrication and reduce time and cost. The MUXED-D scan consists of a D flip-flop and a 2 to 1 multiplexer. Compared to the latest scan cell, we have seen a 25 % decrease in occupied area and 15.62 % decrease in the number of cells and latency from 1 to 0.75 clock cycle. In general, this scan cell circuit is made of 27 cells with an area of 0.03 µm2 and a latency of 3 clock cycles. The proposed shift register includes four scan cells with two inputs which includes main and test signals. In fact, the number of cells used for the last 4-bit serial testable shift register in this design is 324, 0.39µm2 occupied area and the corresponding delay is 6.75 clock cycles. In order to verify this performance, QCA simulator is used.

Analyzing the Impacts of Serial Correlation and Shift on the Streamflow Variability within the Climate Regions of Contiguous United States

The spatiotemporal hydrologic variability over different regions of the contiguous United States poses the risk of droughts and floods. Understanding the historic variations in streamflow can help in accessing future hydrologic conditions. The current study investigates the historic changes in the streamflow within the climate regions of the continental United States. The streamflow records of 419 unimpaired streamflow stations were grouped into seven climate regions based on the National Climate Assessment, to evaluate the regional changes in both seasonal streamflow and yearly streamflow percentiles. The non-parametric Mann–Kendall test and Pettitt’s test were utilized to evaluate the streamflow variability as a gradual trend and abrupt shift, respectively. The Walker test was performed to test the global significance of the streamflow variability within each climate region based on local trend and shift significance of each streamflow station. The study also evaluated the presence of serial correlation in the streamflow records and its effects on both trend and shift within the climate regions of the contiguous United States for the first time. Maximum variability in terms of both trend and shift was observed for summer as compared to other seasons. Similarly, a greater number of stations showed streamflow variability for 5th and 50th percentile streamflow as compared to 95th and 100th percentile streamflow. It was also observed that serial correlation affected both trends and steps, while accounting for the lag-1 autocorrelation improved shift results. The results indicated that the streamflow variability has more likely occurred as shift as compared to the gradual trend. The outcomes of the current result detailing historic variability may help to envision future changes in streamflow. The current study may favor the water managers in developing future decisions to resolve the issues related to the streamflow variability in flood and drought-prone regions.

Hardware design of real-valued NSCT transform for biomedical video compression

Abstract Number based Non-Subsampled Contourlet Transform (NSCT) diminishes the difficulty of the transformation operation kernel in biomedical video compression by dispensing the requirement for floating number mathematics. Yet, the dynamic scope of INSCT is huge and in this manner, equipment cost is more. In this manuscript, an innovative transformation operation kernel for biomedical video compression is projected which utilizes a novel set of complex and real- esteemed -NSCT coefficients. The projected NSCT decreases the equipment cost, area utilized and propagation time by diminishing the complication with intermediary information duration. Proposed transformation can be implemented by digit parallel multiplications and serial shift operations. Thus the itinerant fault can be decreased by standardize this numeral information and shift quantity for Biomedical video compression. Intermediary information duration and area, power consumption of the proposed method is fewer.

Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register

In the emerging nanotechnology, a finest potential alternative to transistor-based technology is Quantum-dot cellular automata (QCA). It promises higher device density and lower power consumption. The predominant application of QCA is the realization of configurable blocks in the digital systems. This paper presents a new serial scan register and a boundary scan cell, essential components used for chip-level and system-level testing. The proposed majority logic gate-based 1-bit clocked D-flip-flop (DFF) and the rotating multiplexer is used in these techniques. In the first attempt, the clocked DFF is further extended to implement the 2-bit, 4-bit, serial shift register and scan flip-flop. The detailed structural and performance analysis in different aspects proves that the proposed circuits offer elevated performance in contrast to earlier reported works. The various circuit comparison factors that are to be considered in QCA are the circuit complexity, area, delay in terms of the number of clocks, and energy dissipation. Significant improvements have been enhanced in the proposed layouts as compared to traditional approaches. In addition, power dissipation analysis of the stated DFF would be carried out at 2 K Temperature using different tunnelling energy levels (0.5, 1.0, and 1.5 Ek). All the simulations are performed using QCA Designer Ver. 2.0.3 and the power analysis is performed by QCA Pro tool Ver. 1.0.

An Efficient Design of Parallel and Serial Shift Registers Based on Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is considered as rising nanotechnology, which offers computer calculations at the stage of nano by employing molecular modules as calculational modules. Employing this engineering leads to lower splinter region along less power dissipation and can remove the spatial constraints of Complementary Metal Oxide Semiconductor (CMOS) procedure. Shift registers generally utilize currents in a smart scheme. Therefore, modeling these constructions, along with higher consistency and strength, is significant. This article uses a robust dual-edge triggered QCA-based D flip flops. Efficient parallel-in-parallel-out (PIPO) and serial input-serial output (SISO) QCA-based shift registers are also introduced. The simulation and functionality of the suggested constructions have been verified with QCA designer, and their credit is also verified. Presented architectures contain proper QCA execution and provide the minimum difficulty and occupy an area rather than previous constructions. These circuits achieve a noticeable improvement in cell number.

4-Bit serial shift register with reset ability and 4-bit LFSR in QCA technology using minimum number of cells and delay

Quantum-dot cellular automata (QCA) nanotechnology is one of the proposed technologies for replacing CMOS technology. Shift registers are one of the important areas in the design of digital circuits and memory structures. Given the importance of shift registers, in this paper, new structures have been proposed for shift registers in QCA nanotechnology. At first, proposed D-latch is presented to be used in the main block of shift registers, which has only 18 cells, a delay of 0.5 cycles and less area than previous designs. Subsequently, a 4-bit series register will be presented using the proposed D-latch, which is at least 30% lower than the previous ones in terms of cell numbers and area. In addition, a reset pin is needed in shift registers which are used in microprocessors. Most of the previous designs did not have the reset pins and therefore a new version of 4-bit shift register which has the reset pin will be presented in this paper. New and former designs have been expanded from 2 bits to 8 bits, and parameters variations are presented in the table and diagrams. The proposed new designs have interesting features in terms of stability, number of cells and occupied area, compared to previous designs that do not have the reset capability. In addition, the proposed shift register is used to design an optimized LFSR circuit in QCA nanotechnology with only 157 cells and 0.2 µm2 area.

Design and Implementation of a Sliding-Mode Controller for Low-Dropout/Linear Regulator

This brief presents an approach to utilize of sliding-mode (SM) controller in digital low-dropout/linear regulators. Various design aspects, including the extraction of the regulator state-space model and sliding coefficients by considering the hitting, existence, and stability conditions are described. Moreover, the freeze control block is introduced as a solution to compensate for the high frequency chattering phenomenon of SM, resulting in reduction of switching losses. In order to verify the statements, a quasi digital low-dropout/linear regulator is implemented in a discrete form on a PCB. The circuit consists of the proposed current-mode current feedback amplifier-based SM controller and switched-mode pMOS array driven by a bidirectional serial shift register, which is controlled by the SM controller. The results reveal that the controller detects the load changes rapidly, and eliminates the output limit-cycle oscillation, providing a robust and stable output voltage.

Qualitative assessment of climate-driven ecological shifts in the Caspian Sea

The worldwide occurrence of complex climate-induced ecological shifts in marine systems is one of the major challenges in sustainable bio-resources management. The occurrence of ecological environment-driven shifts was studied in the Southern Caspian Sea using the “shiftogram” method on available fisheries-related (i.e. commercially important bentho-pelagic fish stocks) ecological and climatic variables. As indicators of potential environmentally driven shift patterns we used indices for the North Atlantic Oscillation, the Southern Oscillation, the Siberian High, the East Atlantic-West Russia pattern, as well as Sea Surface Temperature and surface chlorophyll-a concentration. Given the explorative findings from the serial shift analyses, the cascading and serial order of multiple shift events in climatic-ecologic conditions of the southern Caspian Sea suggested a linkage between external forces and dynamics of ecosystem components and structures in the following order: global-scale climate forces lead to local environmental processes, which in turn lead to biological components dynamics. For the first time, this study indicates that ecological shifts are an integral component of bentho-pelagic subsystem regulatory processes and dynamics. Qualitative correspondence of biological responses of bentho-pelagic stocks to climatic events is one of the supporting evidences that overall Caspian ecosystem structures and functioning might have–at least partially–been impacted by global-scale climatic or local environmental shifts. These findings may help to foster a regional Ecosystem-based Approach to Management (EAM) as an integral part of bentho-pelagic fisheries management plans.

Sensitivity to meter in auditory feedback during music performance.

Performance of a complex sequential task, such as speech or music, occurs simultaneously with its perceived outcome, known as auditory feedback. The importance of auditory feedback to the fluency of performance is demonstrated by the disruptive effects of altered auditory feedback (AAF). For instance, it has been know for decades that sequence production (in music and speech) can be disrupted by delayed auditory feedback (DAF), a slight asynchrony between actions and resulting sounds (for reviews see Finney, 1999; Howell, 2004; Pfordresher, 2006; Yates, 1963). Fluency in performance clearly relies on temporal coordination between planned actions and concurrent sounds. It is less clear whether performance relies on the content of auditory feedback, which in a musical context refers to the pitches associated with individual notes.For some time, it appeared as though performance may not rely on feedback content. For instance, Howell and Archer (1984) found that disruption from DAF was unchanged when speech feedback was converted to an amplitude-modulated square-wave tone. Finney (1997) further demonstrated that pianists' performances of Bach inventions did not suffer when pitch content was altered in a random-like way. These observations are consistent with Howell's claim that DAF effects result from displacement of auditory rhythms, relative to the rhythmic coordination of actions (Howell, 2001, 2004; Howell, Powell, & Khan, 1983; Howell & Sackin, 2002).However, Pfordresher (2003) introduced an AAF manipulation of pitch content that can disrupt production, referred to as a serial shift. In contrast to other manipulations of content, serial shifts involve presenting pitches from a planned melody (i.e., a sequence of actions that are associated with a sequence of anticipated pitch events) at an alternate serial position. For instance, a lag-1 serial shift causes the feedback pitch heard at each keypress to match what the performer produced at the previous keypress. As such the feedback melody is serially shifted relative to the planned melody. Serial shifts lead to increased pitch errors in performance, while sparing produced timing (Pfordresher, 2003), can disrupt performance of both pianists and nonpianists (Pfordresher, 2005), can lead to disruption of music performance via keyboard or singing (Pfordresher & Mantell, 2012), and can also disrupt the accuracy of speech production (Pruitt & Pfordresher, 2015). It is important to note that serial shifts are distinct from traditional DAF, even though serial shifts may refer to previous events. For instance, hearing serially shifted pitches from future positions also disrupts performance (Pfordresher & Palmer, 2006).Although the effect of serial shifts does demonstrate sensitivity to pitch content, this effect alone does not rule out the possibility that their disruptive effect is to some extent based on rhythmic relationships between perception and action. It has often been observed that the patterning of pitch content can convey rhythmic information through melodic accents (Cooper & Meyer, 1960; Ellis & Jones, 2009; Jones, 1987), including breaks or pivots in the melodic contour (for examples, see Handel, 1989, p. 398), and the use of parallelism in broader pitch patterns (Acevedo, Temperley, & Pfordresher, 2014; Deutsch & Feroe, 1981; Steedman, 1977; Temperley & Bartlette, 2002).We adopted these features to create stimuli for the present study. Notation for the four melodies we used are shown in Figure 1 along with their meter, represented as a grid. Metrical accents are associated with positions that have higher columns of X's above them. Melodies were created to match either a binary (4/4) or a ternary (3/4) metrical structure. The first binary melody (Figure IA) used breaks in the melodic contour to signal metrical boundaries, whereas the second binary melody includes a recurring pattern structure based on an alternating melodic contour that is inverted in the second measure. …

Ultra Low Power, High Performance Negative Edge Triggered ECRL Energy Recovery Sequential Elements with Power Clock Gating

Flip flops form an indispensable building block in the design of digital systems. In this study, adiabatic switching technique is used in the design of low-power negative edge triggered energy recovery flip-flops. In particular, the negative edge triggered D, SR and JK flip-flop designs based on the Quasi-adiabatic ECRL (Efficient Charge Recovery Logic) architecture are proposed. The projected design is illustrated with an 8 bit Serial Input and Parallel Output shift register (SIPO). The setup time and hold time are minimal in negative edge triggering compared to the pulsed and positive edge triggering which contributes to the high performance and the signal integrity of the design. Additionally, glitching is avoided due to the edge triggering which in turn reduces the soft error rate in the flip-flops. The simulation results have shown improvements in power efficiency by 95 and 75%, respectively for the D flip-flop and 8 bit shift registers than their CMOS counter parts. Due to its several merits, this design can find many real time applications such as digital communication (cryptography), memories and shift registers in microcontrollers. The four phase power clocks are utilized in the pipelining of the stages of the shift register, which mitigates all the relevant timing problems addressed in the literature of flip flops. For simulation, SPICE EDA simulation environment using the 350 nm process technology library from Austria micro systems have been used.

Multi-bit operations in vertical spintronic shift registers

Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

An Efficient Technique to Protect Serial Shift Registers Against Soft Errors

This brief presents a technique to efficiently correct single soft errors in serial shift registers. The proposed scheme uses two copies of the shift register. To achieve error correction, data are convolutionally encoded at the input of one of the copies and are decoded at its output. This processing ensures that in that copy, any error affecting a single bit will corrupt its output for multiple cycles. On the other hand, a single-bit error in the original copy will corrupt its output only for one cycle. Therefore, the error patterns can be used to identify the copy that has suffered the error and, consequently, to correct the error. The proposed technique has been implemented in a Hardware Description Language and implemented in a 45-nm library. A fault injection tool has been used to evaluate the effectiveness of the proposed scheme, showing that it can correct all single soft errors. The cost of the proposed approach in terms of circuit area has been compared with a traditional triple-modular redundancy implementation. The results show significant cost reductions, which approach a factor of 33% for large shift registers.

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

Deletion of the trpc4 gene and its role in simple and complex strategic learning

AbstractThe TRPC4 ion channel is expressed extensively in corticolimbic and a subpopulation of midbrain dopamine neurons. While TRPC4 knockout (KO) rats exhibit reduced sociability and social exploration, little is known about the role of TRPC4 in motivation and learning. To identify a function for TRPC4 channels in learning processes we tested TRPC4 KO and normal wild type (WT) rats. TRPC4 KO and WT rats exhibited no differences in Y--maze learning or simple discrimination learning. Furthermore, on a more complex serial reversal shift task designed to assess strategic learning where the reward and non--reward cues were repeatedly reversed between training sessions both TRPC4 KO and WT rats performed equally well. Finally, we found no performance differences when using a conditional reversal shift task where a tone signals the reversal of reward and non-reward cues within sessions. These data suggest that although TRPC4 channels may play a role in social interaction/anxiety they exert a minimal role in simple and complex strategic learning.

基于串行最小频移键控的8进制调制的研究

基于串行最小频移键控的8进制调制的研究

Serial Magnetic Resonance Spectroscopy Reveals a Direct Metabolic Effect of Cediranib in Glioblastoma

Proton magnetic resonance spectroscopy is increasingly used in clinical studies of brain tumor to provide information about tissue metabolic profiles. In this study, we evaluated changes in the levels of metabolites predominant in recurrent glioblastoma multiforme (rGBM) to characterize the response of rGBM to antiangiogenic therapy. We examined 31 rGBM patients treated with daily doses of cediranib, acquiring serial chemical shift imaging data at specific time points during the treatment regimen. We defined spectra from three regions of interest (ROI)--enhancing tumor (ET), peritumoral tissue, and normal tissue on the contralateral side (cNT)--in post-contrast T1-weighted images, and normalized the concentrations of N-acetylaspartate (NAA) and choline (Cho) in each ROI to the concentration of creatine in cNT (norCre). We analyzed the ratios of these normalized metabolites (i.e., NAA/Cho, NAA/norCre, and Cho/norCre) by averaging all patients and categorizing two different survival groups. Relative to pretreatment values, NAA/Cho in ET was unchanged through day 28. However, after day 28, NAA/Cho significantly increased in relation to a significant increase in NAA/norCre and a decrease in Cho/norCre; interestingly, the observed trend was reversed after day 56, consistent with the clinical course of GBM recurrence. Notably, receiver operating characteristic analysis indicated that NAA/Cho in tumor shows a high prediction to 6-month overall survival. These metabolic changes in these rGBM patients strongly suggest a direct metabolic effect of cediranib and might also reflect an antitumor response to antiangiogenic treatment during the first 2 months of treatment. Further study is needed to confirm these findings.

IEEE 1149.1의 실시간 신호 시험 구조 설계

보드에 장착된 소자들을 테스트하기위해 제안된 IEEE 1149.1 시험 구조는 입력으로 TDI 핀을 사용하고 출력으로 TDO 핀을 사용하는 커다란 직렬 쉬프트 레지스터이다. IEEE 1149.1은 보드 수준에서의 테스트는 완벽하게 수행하지만 보드가 시스템에 장착되고 난 후의 수행 중인 시스템 수준에서의 실시간 동작클럭 속도로의 테스트에는 문제가 있다. 즉시험대상 핀의 실시간 동작신호를 시험하기 위하여 직렬 시프트 레지스트 체인들의 출력속도를 동작 클럭의 쉬프트레지스터 배수 이상의 속도로 작동 하여야 한다. 본 논문에서는 시스템 클럭과 동일한 속도로 실시간 신호를 캡쳐하기 위한 실시간 신호 시험 구조를 설계하고 시험 절차를 제안하였다. 제안한 실시간 신호 시험 구조를 Altera의 Max+Plus 10.0을 사용하여 제안한 시험 절차에 따라 시뮬레이션을 수행하였으며, 이를 통해 제안한 시험구조가 정확히 동작함을 확인하였다. IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.