This p aper studies the sp eed and hardware performance of the modified fast serial-parallel (MFSP) multip lier with concurrent error detection (CED) by REcomputing with Circularly shifted Operands (RECO) technique. The MFSP multiplier has been proposed primarily to increase the sp eed of the fast serial parallel (FSP)multiplier by using fast parallel adder instead of the parallel ripple carry adder. This multiplier can be used for VLSI when the chip size is limited for high speed applications. By using RECO technique for CED applied to the MFSP multiplier, the copmromise between suitable error coverage, small error latency , suitable multiplication speed improvement and low hardware over-head as possible is exp ected. This multiplier is suitable for VLSI and can be used efficiently In digital signal processing (DSP) applications. Speed and hardware comparisons to the carry save-add shift (CSAS) multiplier with and without RECO technique are also made.