Sequential Processor Research Articles

The reduction of branch instruction execution overhead using structured control flow

This paper presents a technique for specifying change of control (e.g. branch) commands at a sequential processor's macroinstruction set level. It is shown that by representing high level language (HLL) control statements with special machine language instructions, the usual delays associated with control flow changes can be reduced. Preserving the HLL control flow information increases performance by reducing both the number of executed branches and pipeline breaks.

Special computer architectures for image analysis

SUMMARYWith the recent advances of VLSI technology, it has become possible to realize parallel architectures for image processing which are more efficient than the customary sequential processors. The paper discusses general architectural requirements for parallel processing and then the existing systems architectures. This is followed by a description of VLSI devices for image processing in three examples. The paper emphasizes VLSI architectures for image feature extraction, classification and structure (syntax) analysis.

Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model

The implementation of variable addressing and block structure has a substantial influence on the global system performance. One model dederibes this influence as a product of program statistical, architectural and technological parameters, but only for sequential processors. In this correspondence we adapt this model to processors with an instrution prefetch pipeline. An upper and lower bound for the performance measure is obtained, using a best/worst case analysis. The influence of the memory speed on the performance is also determined.

A new distance mapping and its use for shape measurement on binary patterns

The paper describes a new class of distance mappings for binary images, which are based on a border-to-border distance rather than on the distance between an individual point and the border of an object. It is shown how these mappings can be used to calculate efficiently meaningful features like the “line-shapeness” or “compactness” of objects within binary images or to characterize binary images in a global sense. The algorithms involved are well suited for conventional sequential processors.

Basic Techniques for the Efficient Coordination of Very Large Numbers of Cooperating Sequential Processors

Basic Techniques for the Efficient Coordination of Very Large Numbers of Cooperating Sequential Processors

A sequential processor for detecting Gaussian acoustic signals

A sequential approach to detecting Gaussian acoustic signals is discussed. The optimum sequential processor is synthesized and its performance is evaluated. The performance obtained is compared with the performance of the optimum unsequential processor. It is shown that the sequential approach may considerably reduce the required time-bandwidth product when the desired signal is present in the input mixture. However, when the processor receives a noise alone, the time-bandwidth reduction is very small, particularly for high signal-to-noise ratios. Hence, the sequential approach is most promising when one wishes to detect the desired signal (when it appears) as fast as possible but does not mind spending more time when no signal exists.

Simultaneous and sequential processing of information by different hemispheres in animals.

In the experiments on 53 rats, the technique of motion-food conditioned reflexes in combination with unilateral decortication by means of spreading depression was used. Rats were trained in differentiration of geometrical figures united in simultaneous complexes or chain stimuli, presented simultaneously or sequentially. The lateralization of more frequent disruptions was shown to depend, not upon the kind of stimuli used, but upon the character of their presentation. With simultaneous presentation, the greatest disruptions set in after right hemisphere inactivation, but at sequential presentation they were greater as a result of left hemisphere inactivation. It is supposed that animals possess a simultaneous processor in the right hemisphere and a sequential processor in the left one.

A new distance mapping and its use for shape measurement on binary patterns

Abstract The paper describes a new class of distance mappings for binary images, which are based on a border-to-border distance rather than on the distance between an individual point and the border of an object. It is shown how these mappings can be used to calculate efficiently meaningful features like the “line-shapeness” or “compactness” of objects within binary images or to characterize binary images in a global sense. The algorithms involved are well suited for conventional sequential processors.

Hardware Realization of a General Purpose FFT Processor in a Distributed Processing Configuration

An efficient hardware implementation of a 1024-point sequential FFT processor is described. The processor has been configured in a distributed processing system with an INTEL 8086 microprocessor. In case of real signals, it performs a 1024-point transform of two real signals, simultaneously within the same period and subsequently does spectral separation 2.6 msec. Its general purpose capability and the case of interfacing it with standard mini/micro computers are highlighted with a specific illustrations using the INTEL 8086 microprocessor.

Sequential Multistate EMG Signal Processor

A feature of multifunction EMG control is that the operator is always aware when a decision is made. Thus, a sequential processor which observes the EMG signal for the length of time necessary to make a reliable decision would be a logical one. In this paper, two sequential processors are developed for the EMG signal. Exact expressions for the processor performance, error probability, and the average number of samples required to make a decision are derived. The two processors are modeled on a computer and verified experimentally. Both the theoretical and experimental results show that compared to an optimal Bayes receiver the sequential processor, for a given efror probability, requires, on the average, approximately half the number of samples. Finally, a proof is given for the optimum signal set and this set is used in the paper.

Structure of an Ideal Distributed Computer Control System

The problems related to distributed systems belong in general to the crucial ones in the design of computer systems. A general model which simplifies an efficient design of such systems has therefore to include appropriate means to deal with distributed systems.Such a general model is presented here and it is shown, that a high level system, which provides virtually unlimited parallel processing capability independent from geographical distribution can in two steps be mapped to a low level system which only knows sequential processors.

Matching Preferred Cognitive Mode with Teaching Methodology in Learning a Novel Motor Skill

Abstract The purpose of this study was to examine the whole-part methodology issue for teaching physical skills in view of individual differences in the learner's cognitive style. A coeducational pool of 429 undergraduate college students began the study. The Learning Skills Inventory (a modified cognitive map) and the lateral eye movement phenomenon were utilized to identify particular learner characteristics. One hundred subjects were finally classified as either holistic or sequential information processors and completed the study by learning to juggle with either whole or part teaching methods. Using the two-way analysis of variance in a two-by-two factorial design, a significant interaction effect was found (F 1,96 = 6.02, p < .05). Sequential learners using the part method and holistic learners using the whole method took significantly fewer minutes to learn to juggle than sequential learners using the whole method and holistic learners using the part method. Learning efficiency was increased by imp...

Applicability of hybrid simulation

Hybrid simulation means performing simulation by means of hybrid processing with a hybrid processor consisting of a parallel and a sequential processor. To be able to value the applicability of hybrid simulation, it is necessary to have some knowledge about hybrid processing. Parallel and sequential processing are discussed extensively. The computational handicap of the present day generation of a hybrid processor have impeded the applicability of hybrid simulation. The present-day state of the technology is no longer restrictive for the production of a fully automated hybrid processor. Therefore, within a few years the applicability of hybrid simulation will be improved much.

Logic State Analyzers-A New Instrument for Analyzing Sequential Digital Processes

Logic state analyzers are used to monitor, or measure, the sequence of program and data flow in sequential processors, such as computers and microprocessors, as a means of debugging, testing, and troubleshooting these processors. The application of these measurements is discussed using examples of debugging and troubleshooting techniques made possible by logic state analyzers. The capabilities required to implement these measurements are set forth using the previously described measurements. These measurement capabilities, then, become the functional definition of a logic state analyzer. Finally, the block diagram required to implement these measurement capabilities is developed as a further means of describing the measurement of logic or data sequences and the application of these measurements to troubleshooting, debugging, and testing sequential digital machines and systems.

COMPUTER PROCESSING OF AIRBORNE ELECTROMAGNETIC DATA *

AbstractWith the increasing number of channels in AEM systems, computer data handling is becoming a necessity. The experience gained in processing of seismic and aeromagnetic data cannot be applied directly to low‐frequency (100‐5000 Hz) AEM methods. A novel scheme has been designed for AEM data processing and tested on 2900 km (1800 miles) of Input surveys.In the first step, the digital flight tapes are merged with digitized flight path recovery to form the primary data set. The validity of the raw data is controlled by the computer, but the interpreter has an option of checking them in perspective plots of channel amplitudes. The primary data set is reduced by processors which determine the location and type of anomalies and discard noise. Unlike the widely used deconvolution, the sequential processor determines first the anomaly location and then estimates parameters, such as peak amplitude, base width, and excess area, which are used as acceptance criteria. Interpretation parameters, such as σt, conductor depth, and dip are estimated by comparison with quantitative models. The recorded channel amplitudes are plotted together with the selected interpretation parameters in a profile form. The secondary data set which includes only the interpretation parameters for selected anomalies is graphically displayed as a schematic map of apparent σt. Elongated features are traced by a fan strike recognition routine and a trend map is automatically compiled and plotted. Disk storage is essential for second pass processing during which parts of the primary data set are searched for undiscovered anomalies matching the analyzed trend. The suggested procedure for AEM data processing is demonstrated on an Input MK V survey, Southern Indian Lake, Manitoba.

Exact distribution functions of test length for sequential processors with discrete input data

In studies of sequential detection of radar signals, the parameter of primary interest is the length of the sequential test, denoted by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> . Since this test length is a random variable, moments and/or probability distribution functions of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> are desirable. A procedure is described in this communication for obtaining exact probability distribution functions <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P(n)</tex> and exact average values of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> , <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E(n)</tex> , when the input to the sequential processor is discrete radar data (radar data in quantized form). This procedure is based upon the representation of the sequential test as a Markov process. The results are quite general in that they apply to multilevel quantization of the data. However, the procedure appears especially attractive when the number of levels is small as is usually the case when dealing with discrete radar data. The procedure for determining exact distribution functions and average values of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> presented herein is compared with the Wald-Girshick approach for obtaining <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P(n)</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E(n)</tex> , and the superiority of the former approach in computational convenience is indicated.