Fault Simulation For Sequential Circuits Research Articles

Low Power Dissipation and High Fault Coverage Fault emulation of synchronous sequential circuits on FPGA

A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. This paper presents a low hardware overhead test pattern generator (TPG) for Fault Emulation that can reduce switching activity in circuits under test (CUTs) during testing and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed test pattern generation decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed method is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT- RTPG patterns are applied. The proposed approach allows simulation speed-up of 40-500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.

FPGA-based fault emulation of synchronous sequential circuits

A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40–500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.

Path delay fault simulation of sequential circuits

A differential algorithm for concurrent simulation of path delay faults in sequential circuits is presented. The simulator analyzes all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output for vector pairs and considers the hazard states occurring between vectors. The main contribution is in methods of propagating signals between time frames. An optimistic method assumes that all nondestination flip-flops are not affected by delays. The pessimistic method converts all nondestination flip-flops with nonsteady values to the unknown state before these values are propagated beyond the time frame in which a path is activated. A 13-valued algebra is shown to improve the efficiency of fault simulation.

Hybrid Fault Simulation for Synchronous Sequential Circuits

We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.

Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches

The use of three-valued logic for the fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of a high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. Based on this observation, we propose a fault simulation procedure that uses a conventional fault simulation procedure enhanced by a simple implication procedure. The proposed fault simulation procedure identifies faults that are detected under the multiple observation time approach and under a special case of this approach, called the restricted multiple observation time approach. The results of the proposed simulation procedure are compared to the results of a previously proposed procedure to demonstrate its effectiveness. Heuristics to guide a test generation procedure whose test sequences are effective for faults that can only be detected under the multiple observation time approach are also described.

Sequential circuit fault simulation using logic emulation

A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator.

Serial diagnostic fault simulation for synchronous sequential circuits

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is presented. A two level optimization technique has been developed and used to prompt the processing speed. In the high level, an efficient list, which stores the indistinguishable faults, for each fault during the diagnostic fault simulation, and the list maintaining algorithm are applied. Thus the number of fault-pair output response comparisons among all the faults is minimized. In the low level, a bit-parallel comparison is developed to speed up the comparison process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic fault simulator achieves a significant speedup compared to previous methods.

Asynchronous parallel algorithms for test set partitioned fault simulation

We propose two new asynchronous parallel algorithms for test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors. These algorithms provide the same result as the previous synchronous two stage approach. However, due to the dynamic characteristics of these algorithms and due to the fact that there is very minimal redundant work, they run faster than the previous synchronous approach. A theoretical analysis comparing the various algorithms is also given to provide an insight into these algorithms. The implementations were done in MPI and are therefore portable to many parallel platforms. Results are shown for a shared memory multiprocessor.

Diagnostic fault simulation for synchronous sequential circuits

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

Parallel sequence fault simulation for synchronous sequential circuits

A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm successfully extend the parallel pattern method for combinational circuits to sequential circuits by proposing a multiple-pass mechanism to overcome the state dependency in sequential circuits. The fault simulation is performed in parallel by partitioning the entire sequence into subsequences of equal length. Furthermore, techniques are developed to minimize the number of simulation passes. Notably, two compact counters, C x and C d , are proposed to faciliate the early stabilization detection of faulty circuit simulation with minimum space overhead. The experimental results on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator based on ROOFS is 9.16 on average for pseudo random vectors. The parallel sequence algorithm of PSF is especially adaptable to parallel and distributed simulation which exploits sequence partition.

HOPE: an efficient parallel fault simulator for synchronous sequential circuits

HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.

Distributed fault simulation for sequential circuits by pattern partitioning

The authors target the pattern partitioning on the distributed fault simulation because the number of patterns can be reduced by a factor of n, the number of machines, and the faults detected by any machine can be dropped through the communication of the network. For a sequential circuit, there is dependence between test patterns. The state of the circuit depends on the previous patterns applied to the circuit. When the patterns are partitioned into several groups for distributed fault simulation, a sub-fault simulation process for each machine is needed to simulate the circuit into the same state of its previous machine in order to obtain the right results. Hence, in this work, each machine firstly performs the true value simulation with the patterns, which are performed the fault simulation by the previous machines. As the fault simulation is partitioned as above, the state of the good machine is the same as that of the normal fault simulation. A mathematical model is presented to predict the performance of this pattern-partitioning distributed fault simulation. The fault simulator used in is SEESIM, which is a fast sequential circuit fault simulator based on single event equivalence. The statistics of the speedup of the distributed fault simulation with 2000 random patterns and patterns generated by an ATPG, respectively, are shown. It is shown that the speedup ratio increases with the number of machines, and the speedup can exceed the number of machines for some circuits. >

HyHOPE: fast fault simulator with efficient simulation of hypertrophic faults

In sequential circuit fault simulation, hypertrophic faults, which result from lengthened initialisation sequence in faulty circuits, usually produce a large number of fault events during simulation and require excessive gate evaluations. These faults degrade the performance of fault simulators attempting to simulate them exactly. In the paper, an exact simulation algorithm is developed to identify hypertrophic faults and to minimise their effects during fault simulation. The simulator HyHOPE, based on this algorithm, shows that the average speed-up ratio over HOPE for test vectors generated by STG3 is 1.65. Furthermore, the results indicate that the performance of HyHOPE is close to the approximate simulator, in which hypertrophic faults are simply dropped when they become potentially detected.

On fault simulation for synchronous sequential circuits

We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed. >

An observability enhancement approach for improved testability and at-speed test

Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan or silicon-based solutions such as Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed of the circuit. In this paper, a design-for-test method that permits at-speed testing is introduced. The method is based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator. Faults that can be activated but not detected at existing primary outputs are targeted. A minimal set of probe points is selected to detect these faults, and the probe points are compressed to one or two output pins using exclusive-OR trees. The issue of aliasing of fault effects is addressed. Improvements in fault coverage were made for all 17 of the ISCAS89 sequential benchmark circuits studied. Fault coverages between 99% and 100% were obtained for seven circuits, and 100% ATG effectiveness was achieved on all but two circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Path delay fault simulation of sequential circuits

To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transition conditions for two consecutive vectors. After the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flip-flop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The simulation is independent of the specific delays of the combinational elements, and either robust or nonrobust detection can be simulated as options to the user. For robust simulation, an update rule for state variables is proposed whereby a flip-flop is updated with its correct value, provided it is a destination of at least one robustly activated path. This rule gives a higher and more realistic coverage of robustly detected faults. Experimental results verify the effectiveness of the simulator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Delay fault simulation of sequential circuits

This article proposes a 7-valued logic appropriate for test generation and fault simulation, in the area of robust tests for gate delay faults, and a straightforward simulation strategy for sequential circuits. It is shown that a purely qualitative logic of robust testing is inadequate for circuits with edge-triggered flip-flops. The relation between the 7-valued logic and the similar logic proposed before by Smith, Schulz et al., and Lin and Reddy are discussed.

SEESIM: a fast synchronous sequential circuit fault simulator with single-event equivalence

The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.

3-valued trace-based fault simulation of synchronous sequential circuits

An efficient fault simulation algorithm for synchronous sequential circuits is presented. It uses parallel fault simulation with dynamic fault grouping, and combines it with backtracing within certain fanout-free regions and the use of surrogate faults. A backtracing method is developed to handle the three logic values, 0,1, and X, accurately. The concept of surrogate faults is also extended to represent all nine combinations of fault-free and faulty values. The results of simulating a set of benchmark sequential circuits show that reductions in execution time of 7-54% were obtained by the use of backtracing and surrogate faults compared to the well-known method, PROOFS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

PROOFS: a fast, memory-efficient sequential circuit fault simulator

The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits, PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. The fault simulator minimizes the memory requirements, reduces the number of gate evaluations, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs six to 67 times faster on the ISCAS-89 sequential benchmark circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>