Abstract
The use of three-valued logic for the fault simulation of synchronous sequential circuits may incur a loss of accuracy that would cause the fault coverage to be underestimated. In addition, loss of fault coverage may occur due to the test strategy employed. These problems were previously alleviated at the cost of a high computational complexity. We present an observation that allows us to alleviate loss of fault coverage in many cases, at a computational cost similar to conventional three-value fault simulation. Based on this observation, we propose a fault simulation procedure that uses a conventional fault simulation procedure enhanced by a simple implication procedure. The proposed fault simulation procedure identifies faults that are detected under the multiple observation time approach and under a special case of this approach, called the restricted multiple observation time approach. The results of the proposed simulation procedure are compared to the results of a previously proposed procedure to demonstrate its effectiveness. Heuristics to guide a test generation procedure whose test sequences are effective for faults that can only be detected under the multiple observation time approach are also described.
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More From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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